Micron Technology Incorporated

Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Other

Epida Memory, Inc.

Chiaki Dono

Chikara Kondo

Yasuji Koshikawa

Taihei Shido

Seiji Narui

Homare Sato

Hiroki Fujisawa

Shinya Miyazaki

Tomoyuki Shibata

Roman Andreas Royer

Yuki Ebihara

Minehiko Uehara

Seiichi Maruno

Tsugio Takahashi

Masayuki M Nakamura

Masanori Isoda

Hyunui Lee

Toshio Ninomiya

Yuki Nakamura

Jun Suzuki

Hiromasa Noda

Koji Arai

Koji Kuroki

Tomohiko Sato

Takenori Sato

Ryo Fujimaki

Atsushi Fujikawa

Ronny Schneider

Naoya Tanimura

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

Apparatuses and methods for direct access hybrid testing

Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.

Semiconductor memory device

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

Semiconductor layered device with data bus

Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

Replication of a first interface onto a second interface and related systems, methods, and devices

Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

Memory device with write data bus control

Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.

Multiple algorithmic pattern generator testing of a memory device

Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

Shared error detection and correction memory

Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.

Apparatuses and methods for providing clocks to data paths

Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

Semiconductor device having a test circuit

Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

Apparatuses and methods for providing multiphase clock signals

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Tokyo, Japan

Chiaki Dono