Intel Corporation

Chiachen Chou

Christopher J Hughes

Rajat Agarwal

Jong Soo Park

Berkin Akin

Simon C Steely, Jr

Kent D Glossop

Kermin Elliott Fleming, Jr

Pratik M Marolia

Aamer Jaleel

Samantika S Sury

Michael C Adler

Neal C Crago

In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

System, apparatus and method for selective enabling of locality-based instruction handling

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features

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Hillsboro, OR, United States of America

Chiachen Chou