Au Optronics Corporation

Apple Inc.

Delta Electronics, Inc.

Chia-Yu Chen

Hung-Che Ting

Hsueh-Hsing Lu

Fan-Wei Chang

Hui-Ling Ku

Yu-Hung Chen

Yi-Chen Chung

Chi-Wei Chou

Ching-Sang Chuang

Tsung-Hsiang Shih

Shih Chang Chang

Lun Tsai

Liu-Chung Lee

Jung Yen Huang

Chin-Wei Hu

Ting-Kuo Chang

Chieh-Wei Chen

Shinya Ono

Lei Yuan

Tsung-Han Tsai

Doh-Hyoung Lee

Niva A Ran

Takahide Ishii

Po-Chun Yeh

Jiun-Jye Chang

Gwanwoo Park

Yu-Wen Liu

Chuan-Jung Lin

Shou-Wei Fang

Hong-Syu Chen

Chun-Yi Lu

Jen-Yu Lee

Chin Wei Hsu

Themistoklis Afentakis

Chih Pang Chang

Yu Hung Chen

Caleb Coburn

Yin-Chang Liu

Hsuan-Lin Cheng

Cheng-Wei Chou

Chih-Wei Wang

Chang-Ming Lu

Ya-Chen Chuang

Chang Ming Lu

Sheng Hui Shen

Chih-Hung Yu

Kai-Chieh Wu

Xingfeng He

Yung Fong Kao

Chung-Wang Lee

Shih Lun Huang

Hsing-Chuan Wang

Fu-Yu Teng

An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Organic light-emitting diode display with passive leakage-reducing structures

A wireless communication system and method is provided. The wireless communication system includes a wireless transceiver device and a processing device. The processing device includes a direction control module, a power adjusting module and a boundary setting module. The direction control module controls the scanning direction and generates a point direction information record according to each reference position respectively. The power adjusting module adjusts the transmitting power and generates a point power information record according to each reference position and the corresponding point direction information record respectively. The boundary setting module generates a boundary information record. The processing device controls the transmitting direction and the transmitting power according to the point direction information record(s), the point power information record(s) and the boundary information record, so as to limit a transmission of the wireless signal within a specific area.

Wireless communication system and method

A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Electrical components having metal traces with protected sidewalls

The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Array substrate

A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain.

TFT structure and pixel structure

A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Manufacturing method of array substrate

A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.

Thin film transistor, pixel structure and method for fabricating the same

A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Array substrate and manufacturing method thereof

This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.

Transistor with etching stop layer and manufacturing method thereof

A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.

Thin film transistor and fabricating method thereof

A pixel structure of an organic electroluminescence apparatus includes at least an active device connected to a scan line and a data line, a first electrode, a dielectric material layer, a first isolating layer, a second isolating layer, an organic light-emitting material layer and a second electrode. The dielectric material layer is disposed on the first electrode and has a first opening to expose the first electrode. The first isolating layer disposed on the dielectric material layer includes an oxide semiconductor material and has a second opening to expose the first electrode. The second isolating layer is disposed on the first isolating layer and has a third opening to expose the first electrode in the first opening and the first isolating layer in a sidewall of the second opening. The organic light-emitting material layer is in the third opening. The second electrode is on the organic light-emitting layer.

Pixel structure of organic electroluminescence apparatus

A method of fabricating a pixel structure is provided. A gate electrode is formed on a substrate, and a dielectric layer is formed on the gate electrode. A patterned metal oxide semiconductor layer and a patterned metallic etching stop layer are formed on the dielectric layer above the gate electrode. A first conductive layer is formed to cover the patterned metallic etching stop layer and the dielectric layer. The first conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a source and a drain. A second conductive layer is formed to cover the source, the drain and the dielectric layer. The second conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a first electrode layer. The patterned metallic etching stop layer exposed between the source and the drain is removed.

Method of fabricating pixel structure and method of fabricating organic light emitting device

Growing community of inventors

Hsin-Chu, Taiwan

Chia-Yu Chen