Mediatek Corporation

Genesys Logic, Inc.

Chia-Yu Chan

Bo-Wei Hsieh

Shang-Pin Chen

Jou-Ling Chen

Chih-jung Lin

Nei-Chiung Perng

Ching-Yeh Hsuan

Ching-jung Yu

A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.

Delay tracking method and memory system

A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.

Memory device, memory controller and associated memory system operated according to selected clock signals

A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.

Method of parity training for a DRAM supporting a link error checking and correcting functionality

A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.

Memory interface circuit having signal detector for detecting clock signal

A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

Memory interface circuit capable of controlling driving ability and associated control method

An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path.

Growing community of inventors

Kaohsiung, Taiwan

Chia-Yu Chan