Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Yi Su

Harry-Hak-Lay Chuang

Chun-Hung Chen

Chih-Ping Chao

Hua-Chou Tseng

Jye-Yen Cheng

Alex Kalnitsky

Chien-Chih Ho

An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

Growing community of inventors

Yonghe, Taiwan

Chia-Yi Su