Delta Electronics, Inc.

Chia-Yen Lee

Hsin-Chang Tsai

Peng-Hsin Lee

Ming-Wei Tsai

Ching-Tung Hsu

Rong-Chang Liang

Yen-I Chou

Yeong-Feng Wang

Keh-Su Chang

Chia-Hui Chen

Meng-Han Liu

Shiau-Shi Lin

Ming-Hai Chang

Tzu-Hsuan Cheng

Chi-Cheng Lin

Peng-Hisn Lee

Yu-Hsiang Cheng

Ping-Chun Tsai

A method for predicting and compensating frictions of a feed system includes following steps: constantly obtaining current signals and angle-position signals of a motor by a motor driver of a feed system after being activated; calculating frictions of the motor upon each rotating position according to the obtained current signals and angle-position signals and generating multiple records of friction data; creating a friction model according to the multiple records of friction data and the angle-position signals each respectively corresponding to each record of friction data with respect to each rotating position; importing current angle-position signal of the motor to the friction model for predicting a predicted friction; calculating a compensation current based on the predicted friction; and, controlling the motor driver to additionally provide the compensation current to the motor for conquering an upcoming friction of the feed system approximate to the predicted friction.

Method for predicting and compensating frictions of feed system, and computer readable storage

A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Manufacturing method of packaging device

Packaging device and manufacturing method thereof

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Power module package having patterned insulation metal substrate

A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.

Semiconductor device

A semiconductor component comprising a lateral semiconductor device, a vertical semiconductor device, and a leadframe is provided. The lateral semiconductor device has a first side and a second side, and a first electrode, a second electrode, and a control electrode positioned on the first side. The vertical semiconductor device has a first side and a second side, a second electrode and a control electrode of it positioned on the second side and a first electrode of it positioned on the first side. The leadframe electrically and respectively connected to each of the first electrode of the lateral semiconductor device, the second electrode of the lateral semiconductor device, the second electrode of the vertical semiconductor device, and the control electrodes, wherein the first side of the vertical semiconductor device is mounted on the second side of the lateral semiconductor device, and the first electrodes of both devices are electrically connected.

Semiconductor component having a lateral semiconductor device and a vertical semiconductor device

A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.

Method of forming interconnection structure of package structure

Interconnection structure of package structure and method of forming the same

Disclosed is an image display apparatus, including a display device displaying right-eye images and left-eye images. A light-modulating device attached to the display device; and a temperature sensor monitoring the light-modulating device temperature. The light-modulating device deflects the right-eye and left-eye images to an observer's right and left eyes respectively without a temperature variation in the temperature sensor.

Electrically switchable light-modulating cell with via for image display apparatus

A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.

Wafer-level chip scale package

An interconnection structure is provided having a substrate with at least one electric device formed adjacent to a first side of the substrate and a via hole formed therethrough. The via hole has a first opening adjacent to the first side of the substrate. A via structure is disposed in the via hole without exceeding the first opening. A first pad is disposed on the first side of the substrate and covers the via hole. A second pad is disposed on a second side of the substrate opposite to the first side, wherein the via structure extends into the second pad. The first pad is adjoined to the via structure and electrically connects with the at least one electric device, and the first pad has a protrusion portion extending into the via hole.

Interconnection structure having a via structure

The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.

Embedded package structure and method for manufacturing thereof

A 3D image display system with high resolution is disclosed. The system may deflect left and right eye images to a left and right eye of a viewer, respectively. As such, the viewer can see 3D images. With a time-sharing mode, all of electronically switchable light modulating cells are configured to modulate all of the images deflected to the left eye of the viewer during a first period, and modulate all of the images to the right eye of the viewer during a second period, and the first period and the second period are alternate periods. Alternatively, a part of the electronically switchable light modulating cells are configured to modulate left eye images deflected to the left eye of the viewer, and another part of the electronically switchable light modulating cells are configured to modulate right eye images to the right eye of the viewer during the same period.

Growing community of inventors

Taoyuan Hsien, Taiwan

Chia-Yen Lee