Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Yang Hung

Sheng-Liang Pan

Po-Chuan Wang

Huan-Just Lin

Guan-Xuan Chen

Jyu-Horng Shieh

Shu-Huei Suen

Jack Kuo-Ping Kuo

Syun-Ming Jang Jang

Chung-Chieh Lee

Yung-Chang Hsu

Bing-Hung Chen

Yungtzu Chen

Mei-Yun Wang

Fu-Kai Yang

Kuo-Yi Chao

Chao-Hsun Wang

Chen-Yuan Kao

Po-Zen Chen

Chih-Kang Chao

Yu-Feng Yin

Feng-Yu Chang

Shao-Jyun Wu

I-i Cheng

Szu-Hung Yang

Chih-Cherng Jeng

Pang-Sheng Chang

Chia-Sheng Chang

Yung-Tzu Chen

Yung Tzu Chen

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

Soft ashing process for forming protective layer on conductive cap layer of semiconductor device

A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Interconnect structure for semiconductor devices

A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Fin field-effect transistor and method of forming the same

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

DC bias in plasma process

Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Semiconductor devices and methods of manufacture

A method includes forming a gate structure on a semiconductor substrate; depositing a carbon-containing seal layer over the gate structure; depositing a nitrogen-containing seal layer over the carbon-containing seal layer; introducing an oxygen-containing precursor on the nitrogen-containing seal layer; heating the substrate to dissociate the oxygen-containing precursor into an oxygen radical to dope into the nitrogen-containing seal layer; after heating the substrate, etching the nitrogen-containing seal layer and the carbon-containing seal layer, such that a remainder of the nitrogen-containing seal layer and the carbon-containing seal layer remains on a sidewall of the gate structure as a gate spacer.

Semiconductor device and manufacturing method thereof

A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.

Semiconductor device and method

A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Metal contacts on metal gates and methods thereof

An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.

Dry ashing by secondary excitation

The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Dual profile shallow trench isolation apparatus and system

Growing community of inventors

Kaohsiung, Taiwan

Chia-Yang Hung