United Microelectronics Corp.

Chia-Wen Wang

Ping-Chia Shih

Kuo-Lung Li

Meng-Chun Chen

Hsiang-Chen Lee

Wen-Peng Hsu

Chih-Yang Hsu

Chien-Hung Chen

Zi-Jun Liu

Chia-Hui Huang

Chih-Hao Pan

Yu-Chun Chang

Ling-Hsiu Chou

Jen Yang Hsueh

Ling Hsiu Chou

Jen-Yang Hsueh

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Method of programming MLC memory device and related MLC memory device

A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

Semiconductor device

A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

Non-volatile memory device and method for fabricating the same

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Method for fabricating semiconductor structure

A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

Non-volatile memory device with reduced distance between control gate electrode and selecting gate electrode and manufacturing method thereof

Semiconductor structure and method for fabricating the same

The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S) removing the part of the U-shaped ONO structure; (S) removing the photoresist; (S) removing the pad oxide pattern and the top oxide layer; and (S) forming a gate structure.

Method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell

Growing community of inventors

Tainan, Taiwan

Chia-Wen Wang