United Microelectronics Corp.

Chia-Wen Liang

Cheng-Tung Huang

Tzyy-Ming Cheng

Shyh-Fann Ting

Wen-Han Hung

Kun-Hsien Lee

Li-Shian Jeng

Jason Jyh-shyang Jenq

Hal Lee

Chien-Ting Lin

Chun-Hsien Lin

Chan-Lon Yang

Sun-Chieh Chien

Jiunn-Hsiung Liao

Chuan-Fu Wang

Yung-Chang Lin

Shin-Chi Chen

Po-Jui Liao

Shao-Hua Hsu

Guang-Yaw Hwang

Tsung-Lung Tsai

Hung-Ling Shih

Yeng-Peng Wang

Chun-Wen Cheng

Yu-Hsiang Hung

Po-Chao Tsao

Kun-Chi Lin

Der-Yuan Wu

Ming-Tsung Chen

Ming-Te Wei

Chia-Jui Liang

Shin-Chuan Huang

Richard Lee

Neng-Kuo Chen

Sheng-Yuan Hsueh

Yi-Chung Sheng

Tzer-Min Shen

Meng-Yi Wu

Shih-Chieh Hsu

Chih-Chiang Wu

Jing-Yi Huang

Jun-Chi Huang

Ruey-Chyr Lee

Kevin Lin

Jin-Hwa Lee

Vincent Hsueh

Jason Jeng

Jia-Hwa Lee

A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

Semiconductor structure and fabrication method thereof

A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Semiconductor device having metal gate and manufacturing method thereof

A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.

Method of fabricating semiconductor device

A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Method of manufacturing complementary metal oxide semiconductor transistors

A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

Method for forming semiconductor device

A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor

A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.

Static random access memory unit

A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Method of fabricating strained-silicon transistors

A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.

Fabricating method of semiconductor device

A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

Dynamic random access memory cell and method for fabricating the same

A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.

Fuse structure for a semiconductor device

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Hsinchu, Taiwan

Chia-Wen Liang