Mediatek Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Novatek Microelectronics Corp.

Omnivision Technologies, Inc.

National Yang Ming Chiao Tung University

Faraday Technology Corporation

E-pin Optical Industry Co., Ltd.

Chia-Wei Wang

Hung-Jui Kuo

Hui-Jung Tsai

Tai-Min Chang

Yi-Te Chiu

Yu-Tzu Chang

Jau-Jan Deng

Shu-Lin Lai

Shu-Hsuan Lin

Hung-Jen Liao

Hugh Thomas Mair

Hong-Chen Cheng

San-Woei Shyu

Chia-Wei Hsu

Wen-Pin Hsieh

Dao-Ping Wang

Uming Ko

Yun-Chiang Hsu

Joseph Patrick Geisler

Cheng-Hsing Chien

Lee-Kee Yong

Paul William Hollis

Che-Wei Wu

Matthew B Rutledge

Chi-Wei Wang

Shi-Wei Chang

Lee Cheng Hung

Chien-Min Wu

Hsiao-Ping Lin

Shiuhpyng Shieh

Wen-Huang Liu

Tun-Fei Chien

Chi-Yi Hwang

Yu-Ting Liou

Kai-Chung Tsai

Wei-Jr Yang

Chien-Fang Huang

Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant laterally encapsulates the first die. One of the plurality of first die connectors is a taper-shaped die connector. A width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.

Package structure including a die having a taper-shaped die connector

A method for detecting damages of a touch display panel is provided. The touch display panel includes a plurality of sensing pads and a plurality of signal lines. The method includes: selecting at least one first device of the sensing pads and the signal lines as a device under test (DUT); apply a first voltage to the DUT and receiving a feedback signal from the DUT, wherein the feedback signal comprises voltage information or capacitance information of the DUT; and determining whether the DUT is damaged according to the feedback signal.

Method for detecting damages of touch display panel

A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

Semiconductor packages and method of forming the same

A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.

Package structure and method of fabrcating the same

An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.

Integrated circuit, package structure, and manufacturing method of package structure

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

Package structure having at least one die with a plurality of taper-shaped die connectors

An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, and dummy posts. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads. A height of the conductive posts is greater than a height of the dummy posts.

Package structure having taper-shaped conductive pillar and method of forming thereof

Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.

Method of fabricating package structure

Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M&#xd7;1 one-bit memory cells of an array of memory cells and a layout of a second column of M&#xd7;1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M&#xd7;1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M&#xd7;1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Double-pitch-layout techniques and apparatus thereof

In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive.

Integrated circuit package and method

A method for loading a probe card into a prober is provided. The method includes placing a probe card on a carrier plate and analyzing signals produced by two detection sensors. The detection sensor produces the correct signal when the probe card is placed in a normal state, and produces a false signal when the probe card is placed in an abnormal state. In addition, the method includes sending the probe card into the prober in response to the correct signals produced by both detection sensors. Alternatively, the method includes removing the probe card from the carrier plate and placing the probe card on the carrier plate again after adjustment of the probe card in response to a false signal produced by either of the detection sensors.

False detection method for loading probe card

A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

Sense amplifier

A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

Data line control circuit using write-assist data line coupling and associated data line control method

An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.

Embedded memory with setup-hold time controlled internally or externally and associated integrated circuit

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Taichung, Taiwan

Chia-Wei Wang