Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Wei Soong

Hou-Yu Chen

Chih-Pin Tsao

Yong-Yan Lu

Chen Hua Tsai

Jyh-Huei Chen

Shih-Hsun Chang

Shu-Hui Wang

Li-Jung Liu

Yu-Sheng Wu

Jeng-Ya David Yeh

A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.

Method and structure for FinFET devices

A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.

A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure.

Fin field effect transistor (FinFET) device structure and method for forming the same

A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.

In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.

Semiconductor device and manufacturing method thereof

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

Fluorine contamination control in semiconductor manufacturing process

A semiconductor device includes a substrate, an isolation structure over the substrate, and at least one semiconductor layer over the substrate. A first portion of the at least one semiconductor layer is over the isolation structure and a second portion of the at least one semiconductor layer is surrounded by the isolation structure. A doped material layer is between the isolation structure and the second portion of the at least one semiconductor layer.

In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.

A semiconductor device and a method of forming the same are disclosed. The method includes receiving a substrate having a fin projecting through an isolation structure over the substrate; etching a portion of the fin, resulting in a trench; forming a doped material layer on sidewalls of the trench; and growing at least one epitaxial layer in the trench. The method further includes exposing a first portion of the at least one epitaxial layer over the isolation structure; and performing an annealing process, thereby driving dopants from the doped material layer into a second portion of the at least one epitaxial layer. The first portion of the at least one epitaxial layer provides a strained channel for the semiconductor device and the second portion of the at least one epitaxial layer provides a punch-through stopper.

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Taoyuan, Taiwan

Chia-Wei Soong