Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Chia-Wei Huang

Cheng-Cheng Kuo

Yuan-Yao Chang

Yi-Hua Lu

Jing-Sen Wang

Wei-Jhih Wang

Yuan-yao Chang

Hung-Chi Chiu

A transmitter includes a transmitter circuit, a calibration circuit, and a transmitter signal strength indicator circuit. The transmitter circuit is coupled to a power node to receive a supply voltage and transmits an output signal via an antenna. The calibration circuit senses a current of the power node when the transmitter circuit operates in a first frequency band and operates in a second frequency band to generate a signal having different values and generates a calibration signal according to the signals having the different values. The transmitter signal strength indicator circuit detects power of the output signal to generate a first detection signal, and generate a second detection signal according to the calibration signal and the first detection signal. The transmitter circuit adjusts the power of the output signal to be target power according to the second detection signal.

Transmitter and power calibration method

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

Test circuit and method for operating the same

A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.

Method, test line and system for detecting semiconductor wafer defects

Growing community of inventors

Hsinchu, Taiwan

Chia-Wei Huang