United Microelectronics Corp.

Chia-Wei Huang

Ming-Jui Chen

Yung-Feng Cheng

Chun-Hsien Huang

Tan-Ya Yin

Ting-Cheng Tseng

Ching-Wen Hung

Chih-Sen Huang

Yi-Wei Chen

Shih-Fang Tzou

Shu-Ru Wang

Te-Hung Wu

Sheng-Yuan Huang

Pei-Ru Tsai

Po-Chao Tsao

Yu-Tse Kuo

Hsin-Yu Chen

Li-Ping Huang

Kai-Lin Chuang

Ping-I Hsieh

Chien-Heng Liu

Hsin-Jen Yu

Yu-Cheng Tung

Yi-Hui Lee

Jia-Rong Wu

Chia-Lin Lu

Ying-Cheng Liu

Chin-Sheng Yang

Shih-Fang Hong

Ming-Te Wei

Shih-Chun Tsai

Yi-Kuan Wu

Wei-Cyuan Lo

Chuen Huei Yang

Tsung-Yeh Wu

Feng-Yi Chang

Chieh-Te Chen

Chen-Hua Tsai

Cheng-Te Wang

Hui-Fang Kuo

Chuen-Huei Yang

Chih-Hao Wu

Shih-Hsun Kuo

Po-I Lee

Chih-I Wei

A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

Semiconductor device with a single diffusion break structure and a gate structure having aligned sidewalls

Method for fabricating a fin with minimal length between two single-diffusion break (SDB) trenches

Semiconductor device with a single diffusion break structure having a sidewall aligned with a gate sidewall

A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.

Method for generating masks for manufacturing of a semiconductor structure

A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.

Semiconductor device

A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.

Method for generating masks for manufacturing of a semiconductor structure and method for manufacturing a semiconductor structure using the same

A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Static random access memory unit structure

A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.

Method of forming photomask

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.

Semiconductor device and manufacturing method thereof

Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Dummy gate technology to avoid shorting circuit

A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Method of forming semiconductor structure

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

Semiconductor layout structure

Static random access memory layout structure

The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Semiconductor structure and method of forming the same

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Kaohsiung, Taiwan

Chia-Wei Huang