Taiwan Semiconductor Manufacturing Comp. Ltd.

National Applied Research Laboratories

Synopsys, Inc.

National Yang Ming Chiao Tung University

Richwave Technology Corp.

Hongfujin Precision Electronics (Zhengzhou) Co., Ltd.

Datatronics Technology, Inc.

Instrument Technology Research Center

Henan Fuchi Technology Co., Ltd.

Chia-Wei Hsu

Xiong-Fei Yu

Chi On Chui

Yu-Ti Su

Ming-Fu Tsai

Cheng-Hao Hou

Pei Ying Lai

Jam-Wem Lee

Jen-Chou Tseng

Alexander Kalnitsky

Wun-Jie Lin

Bo-Ting Chen

Chien-Yao Huang

Li-Wei Chu

Chia-Jung Chang

Po-Lin Peng

Hsiang-Hui Cheng

Shu-Yu Su

Huan-Neng Chen

Jian-Hao Chen

Chun-Heng Chen

Hui-Cheng Chang

Shao-Yu Li

Kuei-Lun Lin

Chih-Yu Hsu

Chang-Fen Hu

Yen-Lin Liu

Hong-Fa Luan

Jo-Yu Wu

Yung-Hsiang Chen

Chih-Sheng Chen

Wei-Chieh Chiang

Chia-Wei Wang

Ming-Hsun Liu

Kuo-Cheng Huang

Tai-Shan Liao

Chi-Hung Huang

Tsung-Da Lin

Wei-Shun Chuang

Ting-Ming Huang

Wen-Hong Wu

Hsin-Ta Lin

Chiu-Yu Ku

Chih-Sheng Liu

Chi-Wei Wang

Yu-Chi Sung

Shiuhpyng Shieh

Hsiao-Hui Hung

Chia-Hsiang Liao

Ming-Hung Chen

Jen-Yu Wen

Chin-Kuo Su

Tzu-Hsuan Wei

Ching-Hao Chen

Chia-Chuan Hsu

Yu-Hsuan Chao

Pei-Lun Hung

A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Gate structures in semiconductor devices

Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Semiconductor device and method of manufacture

A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.

Method for forming semiconductor structure using fluorine to treat gate stack

A detection device includes a substrate, a light source, a detection module, and a heat dissipation module. The substrate includes a first base plate, a second base plate, and at least one connecting portion connecting the first base plate to the second base plate. The light source is disposed on the first base plate. The detection module is disposed on the second base plate. The first base plate has a first surface towards the at least one connecting portion, and the at least one connecting portion has a second surface towards the first base plate. The second surface is connected to a portion of the first surface. The heat dissipation module is disposed on the at least one connecting portion and/or the second base plate, and the influence of heat on proper operation of the detection device is thus prevented.

Detection device preventing damage to detection module from heat generated by light source

In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Semiconductor device and method

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Low dropout regulator circuits, input/output device, and methods for operating a low dropout regulator

Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Capacitor cell and structure thereof

An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Integrated circuit and method of manufacturing same

A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.

Semiconductor device and method of manufacturing same

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Device and method for operating the same

Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Structure and method for enhancing robustness of ESD device

Growing community of inventors

Taipei, Taiwan

Chia-Wei Hsu