United Microelectronics Corp.

Etron Technology, Inc.

National Cheng-Kung University

Chia-Wei Chang

Chia-Ming Kuo

Yu-Ren Wang

Po-Jen Chuang

Fu-Jung Chuang

Chia-Yuan Chang

Shao-Wei Wang

Der-Min Yuan

Tsai-Yu Wen

Shi-You Liu

Shih-Cheng Chen

Guan-Wei Huang

Feng-Chia Chang

Chih-Huei Hu

Yun-Yu Wu

Fong-Gong Wu

Han-Chi Hsiao

A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

Method for forming semiconductor device

A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Semiconductor device and fabrication method thereof

A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.

Method for fabricating semiconductor device

A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.

Memory access circuit for double data/single data rate applications

A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing 'enabled.' The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents 'turn on', if the input-enabling signal represents &#x201c;enabled&#x201d; and the control signal represents &#x201c;not disabled&#x201d;, the output-enabling signal represents &#x201c;enabled;&#x201d; if the input-enabling signal represents &#x201c;enabled&#x201d; and the control signal represents &#x201c;disabled&#x201d;, the output-enabling signal represents &#x201c;not enabled.&#x201d; The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.

Low-power wire-or matching circuit

A group keypad structure in compliance with a standard keyboard installation includes group keypads corresponding to characters of a standard keyboard input method; for example, the structure includes ten group keypads installed from left to right on a base, and the ten group keypads include characters of 'Q, A, Z', 'W, S, X', &#x201c;E, D, C&#x201d;, &#x201c;R, F, V&#x201d;, &#x201c;T, G, B&#x201d;, &#x201c;Y, H, N&#x201d;, &#x201c;U, J, M&#x201d;, &#x201c;I, K, ,&#x201d;, &#x201c;O, L, .&#x201d; and &#x201c;P, ;, /&#x201d; respectively, and further includes ten numeric characters &#x201c;1&#x2dc;0&#x201d;, so as to achieve the effects of reducing the area of a keyboard, shortening the moving distance of a user's fingers, providing an easy and convenient carry, complying with the user's using habit, and improving the input speed.

Growing community of inventors

Tainan, Taiwan

Chia-Wei Chang