Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Tsung Tso

Chih-Teng Liao

Cheng-Hung Tsai

Xi-Zong Chen

Hsiao Chien Lin

Yi-Wei Chiu

Chun-Hung Liu

Tzu-Chan Weng

Po-Zen Chen

Pin Chia Su

Yu-Li Lin

Hann-Ru Chen

Li Te Hsu

Mei-Jen Wu

Kun-Cheng Chen

Yu-Hsiang Fa

Chen Yung-Chan

Jiun-Hong Lai

A semiconductor device having source and drain regions in a semiconductor substrate, a transistor including a gate electrode over the semiconductor substrate, an isolation structure in the semiconductor substrate adjacent to the transistor, a first inter-dielectric layer (ILD) material over the isolation structure, and a capacitor film stack over the first ILD material that includes an isolation plate over and covering a capacitor plate, and a contact to the capacitor plate.

Semiconductor device with short-resistant capacitor plate

A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

A semiconductor manufacturing tool and process to form semiconductor devices is provided. An edge ring of the semiconductor manufacturing tool comprises a high electron mobility material in order to extend an electrical field and sheath such that curvature from the sheath is moved away from a semiconductor wafer so that an impact from the curvature is reduced or eliminated during an etching process.

Semiconductor device, method and tool of manufacture

A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Controlling system for gate formation of semiconductor devices

A method and system for forming a semiconductor structure includes forming at least one material layer over a substrate. At least one portion of the material layer is etched with at least one first precursor, thereby defining at least one material pattern. Charges attached to the material pattern are removed with at least one discharge gas.

Methods of forming semiconductor structures and systems for forming semiconductor structures

Growing community of inventors

Hsin-Chu, Taiwan

Chia-Tsung Tso