Realtek Semiconductor Inc.

Chia-Tso Chao

Ying-Yen Chen

Po-Lin Chen

Jih-Nung Lee

Wen-Hsuan Hsu

Tse-Wei Wu

Cheng-Yan Wen

An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Electronic device test database generating method and electronic device test database generating apparatus

The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N&#xd7;M records of quiescent DC current (IDDQ) data; generating N reference values according to the N&#xd7;M records, in which each of the N reference values is generated according to M record(s) of the N&#xd7;M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N&#xd7;M records by the reference order so as to obtain reordered N&#xd7;M records; generating an IDDQ range according to the reordered N&#xd7;M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Integrated circuit test method

Growing community of inventors

Hsinchu, Taiwan

Chia-Tso Chao