Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Comp-any Gmbh

Chia-Tien Wu

Shau-Lin Shue

Wei-Chen Chu

Jiann-Tyng Tzeng

Tai-I Yang

Shih-Wei Peng

Hsiang-Wei Liu

Ru-Gun Liu

Cheng-Chi Chuang

Hsin-Ping Chen

Tien-Lu Lin

Yung-Hsu Wu

Chung-Ju Lee

Chih-Liang Chen

Wei-Cheng Lin

Chun-Kuang Chen

Yung-Sung Yen

Chih-Ming Lai

Kam-Tou Sio

Tsai-Sheng Gau

Charles Chew-Yuen Young

Kuei-Shun Chen

Ta-Ching Yu

Hsin-Yen Huang

Hui-Ting Yang

Hai-Ching Chen

Tien-I Bao

Tai-Yen Peng

Shao-Kuan Lee

Cheng-Chin Lee

Yung-Chih Wang

Shun Li Chen

Jye-Yen Cheng

Wei-An Lai

Yu-Chieh Liao

Pokuan Ho

Lei-Chun Chou

Yu-Sheng Chang

Wei-Ling Chang

I-Long Wu

Po-Kuan Ho

Ming-Han Lee

Chung-Hui Chen

Shin-Yi Yang

Chih Wei Lu

Cheng-Hsiang Hsieh

Wei-Hao Liao

Hsiang-Huan Lee

Cheng-Hsiung Tsai

Min Cao

Hsin-Chieh Yao

Guo-Huei Wu

Chia-Wei Su

Yu-Teng Dai

Wan-Te Chen

Jian-Hua Chen

Chia-Yun Wu

Hui-Zhong Zhuang

Hsi-Wen Tien

Te-Hsin Chiu

Ming-Hsien Lin

Kai-Fang Cheng

Hsiao-Kang Chang

Cherng-Shiaw Tsai

Chew-Yuen Young

Kuang-Wei Yang

Jia-Hong Gao

Te-hsin Chiu

Chuan-Pu Chou

Chia-Chen Lee

Hui-Ting Yang′

A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Semiconductor structure with improved heat dissipation

An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Integrated circuit

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Deep lines and shallow lines in signal conducting paths

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.

Semiconductor device including structure connecting frontside and backside metal and method of manufacturing the same

A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Signal conducting line arrangements in integrated circuits

A semiconductor structure including a first conductive layer, a second conductive layer situated above the first conductive layer, and a via extending diagonally between the second conductive layer and the first conductive layer to electrically connect the first conductive layer to the second conductive layer.

Diagonal vias in semiconductor structures

An integrated circuit includes a first conductive structure including a root portion of the first conductive structure, tine portions that are arranged in a first semiconductor layer, a neck portion surrounded by a film structure. The integrated circuit further includes a second conductive structure having first and second portions that are stacked along a first direction. The first portion of the second conductive structure is surrounded by the film structure and the second portion of the second conductive structure is in the first semiconductor layer. A third conductive structure in the integrated circuit has horizontal and vertical structures. The horizontal structure extends in a second semiconductor layer and the vertical structure passes through the second semiconductor layer and the film structure to contact a first conductive rail. The first conductive rail and the tine portions are apart from the horizontal structure along the first direction by a same distance.

An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

Integrated circuit device, method and system

A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell; forming a plurality of first metal strips on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall; and forming a plurality of second metal strips on a third plane over the second plane, wherein the plurality of second metal strips comprise a first second metal strip and a second second metal strip separated from each other by the separating wall.

Method of manufacturing a semiconductor device

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Method of providing a workpiece including low resistance interconnect low-resistance interconnect

A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Semiconductor device and method of manufacture

The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

Hybrid metal line structure

The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

Integrated chip with inter-wire cavities

A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.

Semiconductor structure having deep metal line and method for forming the semiconductor structure

Growing community of inventors

Taichung, Taiwan

Chia-Tien Wu