Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Ta Hsieh

Di-Son Kuo

Hung-Cheng Sung

Yai-Fen Lin

Wen-Ting Chu

Jack Yeh

Chuang-Ke Yeh

Chi-Wei Ho

Chen-Ming Huang

Josh Lin

Chrong Jung Lin

Chrong-Jung Lin

Po-Wei Liu

Yu-Chun Chang

Cheng-Ta Wu

Chi-Hsin Lo

Jong Chen

Jenn Tsao

Juang-Ke Yeh

Ying Ling Tseng

Kuo Wei Wu

Chia-Shiung Tsai

Yun-Chi Wu

Tsung-Hua Yang

Kao-Chao Lin

Chung-Li Chang

Shih-Chang Liu

Yong-Shiuan Tsair

Chih-Wei Hung

Hung-Der Su

Po-Kai Hsu

Shui-Hung Chen

Hsiang-Tai Lu

Chia-Ming Pan

Chieh-Fei Chiu

Luan Conn Tran

Shih-Jung Tu

Nai-Chao Su

Chang-Song Lin

Chuan-Li Chang

Sheng-Wei Tsaur

Jake Yeh

Shih-Ching Lee

Tai-Fen Lin

Din-Son Kuo

Ching-Tzer Weng

Chrong-Jun Lin

Di Son Kuo

Chung-Ker Yeh

Hong-Cheng Sung

Yue-Der Chih

Chun-Hung Lee

Jeff J Xu

Shih-Chi Fu

Feng-Jia Shiu

Shun-Liang Hsu

Tsung-Yu Yang

Cheng-Yuan Hsu

I-Ming Chang

Kuo-Reay Peng

Chun-Pei Wu

Ping-Cheng Li

Tsung-Hao Yeh

Yu-Wen Tseng

Chin-Huang Wang

Der-Shin Shyu

Han-Ping Chen

Hsin-Fu Lin

Yu-Ting Tsai

Yi-Jiun Lin

Jung-Ke Yeh

Sheng-Wei Tsao

Hsiu Ouyang

Chang Song Lin

Yai-Fen Liu

Chuang-ke Yeh

Di-Son Kou

Jaung-Ke Yeh

Yu-ting Tsai

Kao-chao Lin

Chien-Ming Ku

Su-Chang Chen

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Semiconductor-on-insulator (SOI) substrate and method for forming

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a first conductive structure over a substrate. A first intermediate sidewall spacer is formed to surround the first conductive structure. A masking material is formed over the substrate and around the first intermediate sidewall spacer. A part of the first intermediate sidewall spacer protrudes outward from the masking material. The part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.

Semiconductor device and method of manufacturing

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor layer and a gate structure on the semiconductor layer. The gate structure includes a multi-stepped gate dielectric on the semiconductor layer and a gate electrode on the multi-stepped gate dielectric. The multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.

Semiconductor device and method for manufacturing the same

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.

A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Semiconductor structure

A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Semiconductor isolation structure and method of making the same

A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

Semiconductor structure and method for forming the same

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.

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Tainan, Taiwan

Chia-Ta Hsieh