Promos Technologies, Inc

Mosel Vitelic Corporation

Chia-Shun Hsiao

Vei-Han Chan

Chung Wai Leung

Jin-Ho Kim

Zhong Dong

Chuck Jang

Chunchieh Huang

Kuei-Chang Tsai

Barbara Haselden

Ching-Hwa Chen

Daniel Wang

Hsing Ti Tuan

Dong Jun Kim

Chao-chueh Wu

Ming-Huan Tsai

Chih-Yu Lee

George Kovall

Chunyuan Chao

Chung-Wai Leung

Yung-Yi Hsu

Yi-Tsai Yi

Steven Ming Yang

Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Method of forming ONO-type sidewall with reduced bird's beak

A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Method of providing contact via to a surface

A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as NO. In one embodiment, a DCS-HTO film is annealed by heating NO gas to a temperature in the range of about 825&#xb0; C. to about 950&#xb0; C. so as to trigger exothermic decomposition of the NO gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated NO gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.

Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor

Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Use of pedestals to fabricate contact openings

Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height. Additionally, adjacent low and high voltage transistors may benefit from simultaneous formation of their gate dielectrics with use of the radical-based oxidizing method.

Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG

A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

Corner protection to reduce wrap around

Methods for improving quality of semiconductor oxide composition formed from halogen-containing precursor

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Use of multiple etching steps to reduce lateral etch undercut

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Nonvolatile memory structures and fabrication methods

In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( ), and also includes conductive spacers ( ). The spacers increase the capacitive coupling between the floating gate and the control gate ( ).

Nonvolatile memories with floating gate spacers, and methods of fabrication

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

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Cupertino, CA, United States of America

Chia-Shun Hsiao