Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia Shiung Tsai

Chen-Hua Douglas Yu

Hun-Jan Tao

Syun-Ming Jang Jang

Pin-Nan Tseng

Chu Yun Fu

Yuan-Chang Huang

Chung-Kuang Lee

So Wein Kuo

Shing-Long Lee

Jung-hsien Hsu

Tien C Chang

Jiunn-Wen Weng

Ying Yin Wang

A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.

Method of forming dual damascene structure with improved contact/via edge integrity

High selectivity Si-rich SiON etch-stop layer

The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process. The hydrogen ions generated combines with the fluorine contained in the oxide forming HF for etching away the interface between the two different oxide layers where boron ions and phosphorous ions are saturated at such interfaces.

Method for anchoring via/contact in semiconductor devices and devices

A method for creating a tapered profile insulator shape, on an underlying silicon nitride layer, using a photoresist shape as a mask, has been developed. A two step dry etching procedure is used, featuring a first dry etching phase, using an etching chemistry comprised of argon, CHF.sub.3 and CF.sub.4, resulting in a tapered profile insulator shape, underlying the photoresist shape. A second dry etching phase, exhibiting high etch rate selectivity between insulator layer and underlying silicon nitride, via use of an etching chemistry comprised of argon, CHF.sub.3, CH.sub.2 F.sub.2, and CH.sub.3 F, is used to remove residual insulator layer from the underlying silicon nitride layer, without significant attack of the underlying silicon nitride layer.

Method for forming a tapered profile insulator shape

A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer. While etching through the plasma etch method there is adjusted at least one of a first control parameter which controls the first plasma etchant component concentration and a second control parameter which controls the second plasma etchant component concentration to provide through the plasma etch method from the blanket layer a patterned layer with a pre-determined blanket layer to patterned photoresist layer plasma etch selectivity. There is also disclosed an apparatus through which the method may be practiced.

Optical emisson spectroscopy (OES) method for monitoring and controlling

A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

Plasma etch method for forming residue free fluorine containing plasma

A novel bi-layer using a silylation process and anti-reflective coatings are employed for making distortion-free submicrometer photoresist patterns. The method involves forming a multilayer composed of a bottom anti-reflective coating (BARC), a first photoresist layer, a middle anti-reflective coating (MARC), and a silylated second photoresist layer for patterning an underlying electrically conducting layer, such as for FET gate electrodes. The upper photoresist layer is then optically exposed through a mask to form a latent image, and is silylated selectively to form a silicon rich region. The BARC and MARC layers prevent reflected radiation from the underlying structure during the optical exposure, thereby providing a distortion-free latent image. The selective silylation of the latent image portion of the photoresist serves as an excellent etch mask for oxygen plasma etching which is then used to pattern the remaining photoresist layer and anti-reflective coatings. The resulting distortion-free photoresist pattern is then used as an etch mask for etching the underlying electrically conducting layer.

Bi-layer silylation process using anti-reflective-coatings (ARC) for

A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier layers are deposited into contact openings by physical-vapor-deposition(PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in a deposit whose thickness diminishes towards the base of the opening. This causes voids when the opening is subsequently filled by chemical-vapor-deposited(CVD) tungsten as well as potential failure of the barrier material due to inadequate coverage at the base of the opening. The method utilizes a two stage reactive ion etching technique to selectively etch the upper portion of the deposited layer while protecting the lower portion with photoresist. A second deposition of barrier layer material then restores material at the top of the opening while augmenting the thickness at the base. This reduces the negative taper of the opening and allows total filling by the subsequent CVD deposition.

Method for improving conformity and contact bottom coverage of sputtered

A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer. The blanket focusing layer is then etched through the first etch method to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer, where the patterned focusing layer has the reproducible positive taper with respect to the patterned photoresist layer and the blanket target layer. Finally, the blanket target layer is etched through a second etch method to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer, where the patterned target layer has a reproducible second etch bias with respect to the patterned focusing layer, where the reproducible second etch bias does not substantially compensate the reproducible positive taper, and where the width of an aperture within the patterned target layer varies inversely as a function of the thickness of the patterned focusing layer.

0.3 Micron aperture width patterning process

A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is first formed upon a semiconductor substrate a second integrated circuit layer which has formed upon its surface a first integrated circuit layer. Through a first etch method, a partial via is then formed within the first integrated circuit layer to a distance of from about 2500 to about 4000 angstroms above the surface of the second integrated circuit layer. The first etch method is chosen to provide a partial via with substantially parallel sidewalls. Through a second etch method, the partial via is then etched completely through the first integrated circuit layer. The second etch method is chosen to possesses an etch selectivity ratio for the first integrated circuit layer with respect to the second integrated circuit layer of at least about 60:1. The method is preferably employed in forming narrow line-width high aspect ratio vias through insulator layers beneath which reside metal silicide layers formed upon integrated circuit device electrodes within integrated circuits.

Selective reactive Ion etch (RIE) method for forming a narrow line-width

This invention provides a method of forming an attenuating phase shifting rim type photomask and an attenuating phase shifting rim type photomask for use in projection type lithographic apparatus. The photomask is formed by exposing a layer of negative photoresist through a second surface of a transparent mask substrate having a patterned layer of attenuating phase shifting material formed on a first surface of the transparent mask substrate. The exposed and developed photoresist forms a pedestal with sloping sides. A layer of opaque material is vertically anisotropically deposited on the top of the pedestal and that part of the patterned layer of attenuating phase shifting material not shaded by the pedestal. The pedestal and opaque material formed on the top of the pedestal is then removed to complete the mask.

Fabrication of self-aligned attenuated rim phase shift mask

An improved and new apparatus and process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the slurry concentration between the wafer and polishing pad is controlled through the application of an electric field between the wafer carrier and polishing platen, has been developed. The result is an increased polish removal rate and better uniformity of the planarization process.

Chemical/mechanical planarization (CMP) apparatus and polish method

A process for preventing the formation of precipitates on a substrate surface containing Ti (e.g., TiN) after a contact layer (e.g., tungsten layer) etch back. The process involves treating the wafer with an oxygen plasma etch after the tungsten etch back to remove the precursors of a precipitate. The oxygen plasma etch is performed at temperature of about 260.degree. C. and a pressure about 4 torr.

Oxygen plasma etch process post contact layer etch back

The surface of a partially manufactured integrated circuit is cleaned by successive immersions in a series of specially formulated baths. Metallic films deposited on surfaces that have been cleaned in this manner do not exhibit subsequent peeling or blistering and have low electrical contact resistance to the surface onto which they were deposited.

Growing community of inventors

Hsin-Chu, Taiwan

Chia Shiung Tsai