Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Shiung Tsai

Shih-Chang Liu

Yeur-Luen Tu

Chung-Yi Yu

Xiaomeng Chen

Chern-Yow Hsu

Ping-Yin Liu

Cheng-Yuan Tsai

Lan-Lin Chao

Ru-Liang Lee

Chi-Ming Chen

Hsing-Lien Lin

Chung-Yen Chou

Cheng-Ta Wu

Chang-Ming Wu

Yuan-Chih Hsieh

Xin-Hua Huang

Fu-Ting Sung

Po-Chun Liu

Hun-Jan Tao

Ming Chyi Liu

Yuan-Tai Tseng

Jiech-Fun Lu

Wei Cheng Wu

Ming-Chyi Liu

Harry-Hak-Lay Chuang

Yu-Hung Cheng

Chen-Jong Wang

Wen-Ting Chu

Chao-Cheng Chen

Chih-Ming Chen

Jen-Cheng Liu

Yao-Wen Chang

Sheng-Chau Chen

Shih-Chi Fu

Hsun-Chung Kuang

Chun-Wen Cheng

Yu-Jen Wang

Jung-Huei Peng

Kai-Wen Cheng

Alexander Kalnitsky

Ching-Chun Wang

Cheng-Hsien Chou

Bao-Ru Young

Lee-Chuan Tseng

Shih-Wei Lin

Yeong-Jyh Lin

Shau-Lin Shue

Wei-Cheng Wu

Jhy-Jyi Sze

Tzu-Hsuan Hsu

Yu-Wen Liao

Shyh-Fann Ting

Fu-Chih Yang

Chin-Chieh Yang

Shu-Ting Tsai

Chen-Hua Douglas Yu

Jhon Jhy Liaw

Chia-Ta Hsieh

Kuo-Ming Wu

Bruce C S Chou

Chen-Ming Huang

Harry Hak-Lay Chuang

Feng-Jia Shiu

Pinyen Lin

Fu-Liang Yang

Chung-Liang Cheng

Min-Feng Kao

Feng-Chi Hung

Huan-Just Lin

Shou-Gwo Wuu

Chii-Ming M Wu

Hung-Cheng Sung

Shang-Ying Tsai

Hai-Dang Trinh

Chun-Chieh Lin

Huang-Lin Chao

Tsung-Yu Chen

Hung-Chang Hsieh

Min-hwa Chi

Chung-Shi Liu

Dun-Nian Yaung

Syun-Ming Jang Jang

Jhon-Jhy Liaw

Chi-Wen Liu

Kuo-Chi Tu

Hsin-Chang Lee

Anthony Yen

Li-Te S Lin

Jyu-Horng Shieh

Szu-Ying Chen

Jing-Meng Liu

Chen-Cheng Kuo

Chun-Wei Chang

Jiun-Lei Jerry Yu

Yung-Chang Chang

Neng-Kuo Chen

Chih-Chiang Tu

King-Yuen Wong

Yun-Yue Lin

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Method to reduce breakdown failure in a MIM capacitor

A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Thin film transfer using substrate with etch stop layer and diffusion barrier layer

A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Photonic semiconductor-on-insulator (SOI) substrate and method for forming the photonic SOI substrate

A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Capacitor structure and method of making the same

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Manufacturing method of semiconductor device

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A select gate and a memory gate are arranged over the substrate. An inter-gate dielectric structure is arranged between the memory gate and the select gate. A conductive contact is disposed on the source/drain region and vertically extends from a bottom of the select gate to a top of the select gate. The select gate is closer to the conductive contact than the memory gate. The select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate. The first outermost sidewall is taller than the second outermost sidewall.

Split gate memory device and method of fabricating the same

A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Memory devices and method of fabricating same

The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

Deposition system for high accuracy patterning

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Integrate rinse module in hybrid bonding platform

In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Embedded backside memory on a field effect transistor

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Method for forming a semiconductor-on-insulator (SOI) substrate

The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Multi-function substrate

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Buffer layer(s) on a stacked structure having a via

A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

Method for forming semiconductor-on-insulator (SOI) substrate by cleaving a multilayer structure along voids to separate a substrate

Growing community of inventors

Hsin-Chu, Taiwan

Chia-Shiung Tsai