Macronix International Co., Ltd.

Chia-Shing Chen

Mam-Tsung Wang

Ming-Hung Chou

Ying-Che Lo

Ming-Shang Chen

Wenpin Lu

Kuen-Long Chang

Ray-Lin Wan

Tom D Yiu

Fuchia Shone

Tzeng-Huei Shiau

I-Long Lee

Yuan-Chang Liu

Hun-Song Chen

A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The presence of asymmetric source and drain diffusions formed thereby improve the isolation between adjacent memory cells and minimizes the disturb problem.

Method for fabricating asymmetric virtual ground P-channel flash cell

A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (2) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gates on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned adjacent the first column and displaced from the second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip, aligned with the first dopant strip and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The manufacturing method of the present invention results in a cell, which increases floating gate memory array density and programming speed while reducing power consumption and the likelihood of a disturb condition.

Method for forming asymmetric flash EEPROM with a pocket to focus

A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.

Method and circuit for substrate current induced hot e-injection (SCIHE)

Method and circuit for substrate current induced hot e.sup.- injection

Method for writing data to a NOR-type flash memory array including loading page data to a bit-latch buffer, programming cells to low threshold voltage V.sub.t, and programming cells to high V.sub.t. Programming cells to high V.sub.t by either: Channel Hot Electron Injection (CHEI) or Source Side Injection (SSI). CHEI releases the band-to-band induced hot hole damage while SSI further reduces the sector size to be the same as page size for NOR-type flash EEPROM memory.

Method for flash EEPROM data writing

A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (2) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating pates on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned adjacent the first column and displaced from the second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip, aligned with the first dopant strip and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The manufacturing method of the present invention results in a cell, which increases floating gate memory array density and programming speed while reducing power consumption and the likelihood of a disturb condition.

Asymmetric flash EEPROM with a pocket to focus electron injection and a

Asymmetric virtual ground p-channel flash cell with latid n-type pocket

Method and system for soft programming algorithm

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Hsing Chu, Taiwan

Chia-Shing Chen