Motorola Corporation

Chia-Shiann Weng

Peter C Curtis

Donald C Anderson

Walter U Kuenast

Paul M Astrachan

Kenneth C Weng

Jose G Corleto

Richard L Greene

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

Data processor with an efficient bit move capability and method therefor

A circular buffer address generation unit (630) may be accomplished by first determining a potential next address (635) based on a current address (644) and an address offset value (646). Having established the potential next address (635), the potential next address (635) is compared with an ending address (640) of the circular buffer. When the potential next address compared favorably with the ending address, use the potential next address as a new address (650), otherwise generate the new address (650) from a beginning address (642) of the circular buffer.

Method and apparatus for generating a circular buffer address in

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

DSP co-processor for use on an integrated circuit that performs multiple

An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.

Integrated circuit that performs multiple communication tasks

Tone detection may be accomplished by receiving an in-phase signal component 203 and a quadrature signal component 204. These components are then sampled to produce a plurality of sampled in-phase signal components 207 and a plurality of sampled quadrature signal components 208. The sampled in-phase signal components 207, or the sampled quadrature signal components 208, are then shifted by a pre-determined phase angle to produce a plurality of shifted components. Having shifted these signals, the shifted signals, or at least a set of them, are compared with the opposite non-shifted sampled signals, or a set thereof. When each of the shifted signal components substantially match the opposite non-shifted signal components, a tone signal is being received.

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Austin, TX, United States of America

Chia-Shiann Weng