Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia Ping Lo

Yee-Chia Yeo

Ziwei Fang

Weng Chang

Yu-Ting Lin

Liang-Gi Yao

De-Wei Yu

Lun-Kuang Tan

Sheng-Wen Chen

Yan-Hua Lin

Shih Yu-Shen

Mei-Yun Wang

Chii-Ming M Wu

Da-Wen Lin

Jerry Lai

A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.

Method of semiconductor integrated circuit fabrication

A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.

Contact silicide having a non-angular profile

A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.

A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.

Flash anneal for a PAI, NiSi process

Growing community of inventors

Jhubei, Taiwan

Chia Ping Lo