Chunghwa Picture Tubes, Ltd.

Chia-Nan Shen

Hsi-Ming Chang

Chia-Chien Chen

Bing-Wei Wu

Wen-Chun Yeh

Hung-Chi Liao

A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer is formed on the substrate, and a first and a second gate are formed thereon. A sacrificed layer is formed on the substrate and a photo-resist layer is formed thereon. The sacrificed layer above the first poly-silicon island is removed by using the photo-resist layer as a mask. A first ion implantation process is performed to form a first source/drain. The photo-resist layer is removed and a second ion implantation process is performed to form a second source/drain. At the same time, the second ion implantation process is used to implant ions into the buffer layer below the two sides of the second gate. A lightly-doped ion implantation process is performed after removing the sacrificed layer.

Manufacturing method of thin film transistor including implanting ions through polysilicon island and into underlying buffer layer

A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed over the substrate to cover the gate and the gate insulating layer. An ion implanting process is carried out to form a source/drain in the polysilicon island beside the gate, wherein a region between the source and the drain is a channel. After the first passivation layer is removed, a patterned dielectric layer is formed over the substrate, wherein the dielectric layer exposes a portion of the source/drain. A source/drain conductive layer is formed over the dielectric layer and is electrically connected to the source/drain.

Method of manufacturing a thin film transistor

A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

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Taipei County, Taiwan

Chia-Nan Shen