Taiwan Semiconductor Manufacturing Comp. Ltd.

Lite-on Technology Corporation

Chia-Ming Hung

Hsiang-Fu Chen

Wen-Chuan Tai

Hsin-Ting Huang

Shao-Chi Yu

I-Hsuan Chiu

Yao-Te Huang

Chang-Yi Yang

Tien-Kan Chung

Yuan-Chih Hsieh

Hung-Hua Lin

Shang-Ying Tsai

Allen Timothy Chang

Chia-Pao Shu

Chia-Hua Chu

Chung-Hsien Lin

Chin-Min Lin

Alex Kalnitsky

Hung-Sen Wang

Jung-Huei Peng

Kuei-Sung Chang

Xin-Hua Huang

Bruce C S Chou

Kuan-Chi Tsai

Yi Heng Tsai

Kang-Yi Lien

Li-Chun Peng

Yi-Chieh Huang

Chun-Wen Cheng

Jen-Yuan Chang

Chi-Yuan Shih

Shih-Fen Huang

Jiou-Kang Lee

You-Ru Lin

Fan Hu

Ching-Kai Shen

Ming-Hung Huang

Ching-Hsien Lin

Te-Hsi Lee

Sheng Kai Yeh

Chu-Heng Chen

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

Semiconductor device and manufacturing method

A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.

Semiconductor device and method of manufacture

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition. A second functional structure overlies the second movable membrane, where the second functional structure is laterally spaced from the first functional structure, and where the second functional structure comprises a second material having a second chemical composition different than the first chemical composition.

Semiconductor device comprising different types of microelectromechanical systems devices

Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

Dielectric protection layer configured to increase performance of mems device

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.

Semiconductor device having microelectromechanical systems devices with improved cavity pressure uniformity

A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

Bond wave optimization method and device

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Conductive bond structure to increase membrane sensitivity in MEMS device

Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.

Semiconductor arrangement and formation thereof

A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to some embodiments of the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.

Method for sealing a cavity of a microelectromechanical systems (MEMS) device using a seal layer covering or lining a hole in fluid communication with the cavity

The present disclosure provides a semiconductor device, which includes a first substrate comprising an upper surface and a second substrate disposed over the first substrate. The semiconductor device also includes a first electrode disposed in the second substrate and configured to move in a direction substantially parallel to the upper surface in response to a pressure difference, and a second electrode disposed in the second substrate. The second electrode is configured to provide a capacitance in conjunction with the first electrode.

MEMS device with enhanced sensing structure and manufacturing method thereof

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Taipei, Taiwan

Chia-Ming Hung