Cirrus Logic Inc.

Micron Technology Incorporated

Genesis Microchip Corporation

Samsung Semiconductor Inc.

Samsung Electronics Co., Ltd.

Chia-Lun Hang

Jih-Hsien Soong

Tzoyao Chan

Osamu Kobayashi

Ali Noorbakhsh

Chih-Ta Sung

Richard Chang

Yuanyuan Sun

A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

Transparent SDRAM in an embedded environment

Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.

Display unit storing and using a cryptography key

A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers. The four output data registers are for storing outputs of the four input registers received through an encoder (234). The output multiplexer is for selecting an output of one of the output registers. For AT-type platforms, up to two adjacent words are packed into one 32-bit doubleword for output. For PC and XT type platforms, up to four adjacent bytes are packed into one 32-bit doubleword for output. The PACs are also compatible with computers having EISA or PCI buses. During 32-bit EISA or PCI bus cycles, the input doubleword is furnished as the output doubleword.

Method and apparatus for packing digital data

A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Memory controller for decoding a compressed/encoded video data frame

A method and apparatus for automatically synchronizing the polarity of video signals generated by a graphics controller card to a display monitor is described. The present invention includes hardware circuitry comprising a storage unit, a detection unit, a selection unit that store, detect, and select input video signals, particularly a vertical and a horizontal synchronization signals, with the same or different polarity that are received from the graphics controller to a display monitor. The present invention synchronizes the polarity of input vertical and horizontal synchronization signals from the graphics controller prior to transmitting the sync signals to the display monitor. The detect and selection circuits of the present invention enable polarity of input sync signals to be synchronized without the use of software as practiced in the prior art.

Polarity synchronization method and apparatus for video signals in a

A page in, burst-out FIFO buffer that stores only words in a single page and transfers the words to a DRAM utilizing a page mode transfer to increase data throughput and decrease latency offloading DRAM bandwidth.

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Morgan Hill, CA, United States of America

Chia-Lun Hang