Macronix International Co., Ltd.

Chia-Ling Lu

Tao-Cheng Lu

Chun-Hsiang Lai

Shih-Yu Wang

Yen-Hung Yeh

Yan-Yu Chen

Yu-Lien Liu

Shin Su

Meng-Huang Liu

Che-Shih Lin

An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

ESD tolerant I/O pad circuit including a surrounding well

An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.

Electrostatic discharge protection circuit

A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

Methods and structures for electrostatic discharge protection

An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

Electrostatic discharge protectors having increased RC delays

A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

Structures for lowering trigger voltage in an electrostatic discharge protection device

An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), and in some embodiments a second silicon controlled rectifier, and a parasitic diode. The silicon rectifiers as well as the parasitic diode can all be formed using a single well formed in a substrate. Further, the ESD protection circuit can be used in systems that have multiple power sources regardless of the difference in voltage between the power sources.

Methods and apparatus for electrostatic discharge protection in a semiconductor circuit

In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad

An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

Electrostatic protection circuit

An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is coupled to a first power source, and the gate of the second silicon controlled rectifier is also coupled to the first power source line.

Electrostatic discharge protection circuit and semiconductor circuit therewith

An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

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Hsinchu, Taiwan

Chia-Ling Lu