Applied Materials, Inc.

Chia-Ling Kao

Sean S Kang

Srinivas D Nemani

Anchuan Wang

Nitin K Ingle

Mehul B Naik

He Ren

Zhijun Chen

Zihui Li

Karthik Janakiraman

Rui Cheng

Takehito Koshizawa

Nikolaos Bekiaris

Krishna Nittala

Kang-Lie Chiang

Jeremiah T Pender

Jeremiah T P Pender

Kwang-Soo Kim

Russell Chin Yee Teo

Chih-Yang Chang

Xiawan Yang

Lina Zhu

Menghui Li

Ming-Yuan Chuang

Susumu Shinohara

Juan Guo

Qu Jin

Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.

Integration processes utilizing boron-doped silicon materials

Exemplary etching methods may include flowing a hydrogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into the substrate processing region. The methods may include contacting a substrate housed in the substrate processing region with the hydrogen-containing precursor and the fluorine-containing precursor. The substrate may define a trench. A spacer may be formed along a sidewall of the trench, and the spacer may include a plurality of layers including a first layer of a carbon-containing material, a second layer of an oxygen-containing material, and a third layer of a carbon-containing material. The second layer of the spacer may be disposed between the first layer and third layer of the spacer. The methods may also include removing the oxygen-containing material.

Systems and methods utilizing solid-phase etchants

Exemplary etching methods may include flowing a hydrogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into the substrate processing region. The methods may include contacting a substrate housed in the substrate processing region with the hydrogen-containing precursor and the fluorine-containing precursor. The substrate may define a trench, and a layer of an oxygen-containing material may be disposed within the trench and exposed on the substrate. The methods may include halting delivery of the hydrogen-containing precursor. The methods may also include removing the oxygen-containing material.

Self-limiting selective etching systems and methods

Embodiments of the present technology may include a method of etching. The method may include flowing a gas through a plasma to form plasma effluents. The method may also include reacting plasma effluents with a first layer defining a first feature. The first feature may include a first sidewall, a second sidewall, and a bottom. The first sidewall, the second sidewall, and the bottom may include the first layer. The first layer may be characterized by a first thickness on the sidewall. The method may further include forming a second layer from the reaction of the plasma effluents with the first layer. The first layer may be replaced by the second layer. The second layer may be characterized by a second thickness. The second thickness may be greater than or equal to the first thickness. The method may also include removing the second layer to expose a third layer.

Methods for anisotropic control of selective silicon removal

Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Methods for barrier layer removal

Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Methods for etching a dielectric barrier layer in a dual damascene structure

Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiF. The etching also involves forming an SiOpassivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOpassivation layer protects the low-k dielectric film during the removing.

Method of removing a metal hardmask

Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF, H, and a diluent inert gas composition.

Method of fabricating an ultra low-k dielectric self-aligned via

Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O/N/SiF. The method also involves etching a portion of the low-k dielectric layer.

Method of patterning a low-k dielectric film

A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.

Delicate dry clean

Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.

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San Jose, CA, United States of America

Chia-Ling Kao