Macronix International Co., Ltd.

National Taiwan University

Intel Corporation

Mediatek Corporation

Institute for Information Industry

Toshiba Global Commerce Solutions Holdings Corporation

Chia-Lin Yang

Hsiang-Pang Li

Ren-Shuo Liu

Po-Han Wang

Cheng-Hsuan Li

Hsiang-Yun Cheng

Ye-Jyun Lin

Shih-Lien L Lu

Hung-Sheng Chang

Han-Wen Hu

Yi-Sheng Lee

Wei-Yi Hsuan

Ming-Liang Wei

Yu-Jung Cheng

Cheng-Yuan Wang

Bo-Rong Lin

Te-Chia Tsai

Ying-Chen Lin

Kin-Chu Ho

Meng-Yen Chuang

De-Yu Shen

Tzu-Hsien Yang

I-Ching Tseng

Nai-Jia Dong

Shang-Xuan Zou

A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Memory system for maintaining data consistency and operation method thereof

A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

Computation method and apparatus exploiting weight sparsity

Examples provided herein describe a female connector in a computing device that includes a plurality of sensors for determining if a male connector has established a proper connection with the female connector. To do so, in one example, each of the sensors is coupled to an actuator that protrudes into an aperture defined by an inner surface of the female connector. As the male connector is inserted into this aperture, the actuators are pressed down which activates the sensors. Furthermore, the actuators are arranged such that a first actuator is deeper within the aperture than a second actuator. Thus, if the male connector pressed down the first actuator but not the second, a computing device can determine that only a partially connection was made. By using at least two actuators arranged at different depths in the aperture, the computing device is able to detect a proper or improper connection.

Detecting a proper connection

A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.

Method for managing a last level cache and apparatus utilizing the same

A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.

Data processing method and system with application-level information awareness

Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed.

Data movement in memory devices

In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein.

Caching method and data storage system capable of prolonging service lifetime of a cache memory

An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Storage device and operating method thereof

The present disclosure relates, according to some embodiments, to a data writing method in a storage system. The method comprises receiving data by the storage media controller, reading a non-volatile memory operation mode in the memory unit by a central control unit, in which the mode corresponds to a data reliability lower than the data reliability requirement of the storage system, reading a data reliability reduction condition in the memory unit by the central control unit, determining whether a system information related to the data meets the condition by the central control unit, and controlling the media control unit to write the data into the non-volatile memory according to the mode by the central control unit when the system information meets the condition.

Flash memory storage system and access method

A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Memory with multiple levels of data retention

The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Growing community of inventors

Taipei, Taiwan

Chia-Lin Yang