United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Lin Hsu

Teng-Chun Tsai

You-Hua Chou

Yu-Hung Lin

Chun-Yuan Wu

Po-Cheng Huang

Chih-Wei Chang

Chih-Chien Liu

Chin-Cheng Chien

Chin-Fu Lin

Sheng-Hsuan Lin

Yu-Ti Su

Chih-Hsun Lin

Yen-Ming Chen

Chun-Wei Hsu

Chang-Hung Kung

Yung-Lun Hsieh

Chin-I Liao

Chien-Hao Chen

Yu-Ting Li

Shao-Chung Hu

Bo-Syuan Lee

Hsueh-Chung Chen

Shih-Hsun Hsu

Ming-Fu Tsai

Yung-Tsung Wei

Ming-Yen Li

Yen-Ting Chen

Jie-Ning Yang

Wu-Sian Sie

Ren-Peng Huang

Chun-Hsiung Wang

Chien-Ting Lin

Kuo-Ji Chen

Wei-Jung Lin

Hsien-Ming Lee

Ming-Sheng Yang

Hon-Lin Huang

Shih-Chi Lin

Ji-Cheng Chen

Mei-Hui Fu

Yi-Liang Liu

Yi-Fang Cheng

Cheng-Chang Wei

Art Yu

Tzu-Cheng Kao

Wei-Che Tsao

Hsin-Huei Wu

Lee-Chun Chen

Yi-Chien Yang

Ken-Hao Fan

Yi-Wei Chen

Chan-Lon Yang

Wun-Jie Lin

Shih-Fang Tzou

Po-Chao Tsao

I-Ming Tseng

Chen-Yi Lee

Kun-Hsien Lin

Hsin-Fu Huang

Rai-Min Huang

Zhi-Cheng Lee

Che-Hua Hsu

Min-Chuan Tsai

Yi-Wen Chen

Chia-Lung Chang

Cheng-Guo Chen

Po-Jui Liao

Wen-Chin Lin

Shao-Hua Hsu

Guang-Yaw Hwang

Jen-Chieh Lin

Tzung-Ying Lee

Yu-Hung Yeh

Hsin-Kuo Hsu

Tsung-Lung Tsai

Min-Chung Cheng

Hung-Ling Shih

Jung-Tsung Tseng

Ya-Hsueh Hsieh

Chih-Hsien Chen

Chia-Hsi Chen

Chia-His Chen

Min-Ying Hsu

Wen-Chieh Su

Yi-Hsiung Lin

An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.

Integrated circuit protection device and method

A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.

Snapback electrostatic discharge (ESD) circuit, system and method of forming the same

An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Electrostatic discharge circuit and method of operating same

An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Power clamp

An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.

Method for detecting environmental parameter in semiconductor fabrication facility

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Low-k dielectric damage prevention

A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.

A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

Semiconductor device and method for fabricating the same

Metal gate formation methods are disclosed herein for providing metal gates with low work function to enhance semiconductor field effect transistor performance. An exemplary method includes forming a gate dielectric layer on a substrate and a barrier layer over the gate dielectric layer. An outer surface of the barrier layer is treated to increase its roughness. After the outer surface of the barrier layer is roughened, a metal layer is deposited over the barrier layer.

Structure and method for metal gates with roughened barrier layer

A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Composite contact plug structure and method of making same

A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

Growing community of inventors

Tainan, Taiwan

Chia-Lin Hsu