Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Chia-Lin Chen

Shih-Chang Chen

Chien-Hao Chen

Tze-Liang Lee

Liang-Gi Yao

Vincent Chang

Mo-Chiun Yu

Ju-Wang Hsu

Ming-Chen Chen

Chi-Chun Chen

Yi-Miaw Lin

Ji-Yi Yang

Pei-Chun Liao

Tze Liang Lee

Sheng-Hui Liang

Chia-Shiung Tsai

Yeur-Luen Tu

Yu-Jen Wang

Mong-Song Liang

Chern-Yow Hsu

Hsing-Lien Lin

Shin-Cheng Lin

Chih-Wei Yang

Chi-Hsin Lo

Yuan-Hung Liu

Tuo-Hung Hou

Chih-Ta Wu

Ming-Fang Wang

Kwang-Ming Lin

Yung-Fong Lin

Cheng-Wei Chou

Chin-Yuan Ko

Chung Chien Wang

Cheng-Tao Chou

Tien-Chih Chang

Jau-Jey Wang

Kuen-Chyr Lee

Ming-Chih Tsai

Yeou-Ming Lin

Ting-En Hsieh

Chia-Ming Hsu

Huang-Lang Pai

Jason Lee

Min-jan Chen

Chi-Fu Lee

Yi-Han Huang

Shu-Wen Chang

Lucy Chang

A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Semiconductor structure

A reliability determination method, which is configured to test a batch of semiconductor devices, includes: obtaining a Welbull distribution of lifetime of the batch of semiconductor devices; dividing the Welbull distribution into at least a first section and a second section, wherein the first section and the second section meet a confidence interval; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, in which the first trend line has a first slope and the second trend line has a second slope; determining the first slope exceeds a second slope; and determining a predicted reliability of the batch of the semiconductor device under a target quality level according to the first section.

Reliability determination method

A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

MIM capacitors with improved reliability

Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

Laminated silicon gate electrode

An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transistors for a stress period t. The stress bias voltage is sufficient to cause a 10% degradation in a drive current of the transistor within the stress period t. A processor is provided for estimating a negative bias temperature instability (NBTI) lifetime &#x3c4; of the transistor based on a relationship between the gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors. The relationship is determined from data observed while applying the single stress bias voltage.

Apparatus for NBTI prediction

A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime &#x3c4; of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Method of NBTI prediction

A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Selective CESL structure for CMOS application

The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, the second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.

Method for determining time dependent dielectric breakdown

A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Method for testing semiconductor devices

A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

STI liner modification method

A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Selective nitride liner formation for shallow trench isolation

A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

Method for forming high selectivity protection layer on semiconductor device

A method includes measuring a gate leakage current of at least one transistor. A single stress bias voltage is applied to the at least one transistor at a given temperature for a stress period t. The stress bias voltage causes a 10% degradation in a drive current of the transistor at the given temperature within the stress period t. A negative bias temperature instability (NBTI) lifetime &#x3c4; of the transistor is estimated based on the measured gate leakage current and a relationship between drive current degradation and time observed during the applying step.

A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 &#x212b; per minute using the same etchant.

Semiconductor device and method of making the same

A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

Semiconductor device having a random grained polysilicon layer and a method for its manufacture

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Hsinchu, Taiwan

Chia-Lin Chen