Realtek Semiconductor Inc.

Dell Products Inc.

Infineon Technologies North America Corp.

Infineon Technologies Ag

Infineon Technologies LLC

Realter Semiconductor Corp.

Chia-Liang (Leon) Lin

Gerchih Chou

Chi-Kung Kuan

Fei Song

Poh-boon Leong

Hong-Yean Hsieh

Serkan Sayilir

Ting-Hsu Chien

Poh Boon Leong

Chao-Cheng Lee

I-Chang Wu

Hong Yean Hsieh

Wen-Juh Kang

Yu Zhao

Jui Chin Fang

Pei-Chieh Hsiao

Hsin-Che Chiang

Heng-Cheng Yeh

Sriram Venkatesan

Chi-Kung (Richard) Kuan

Gerchih (Joseph) Chou

Adolfo Sandor Montero

Timothy Carlyle Shaw

Richard Christopher Thompson

Geroncio Ong Tan

Chih-Hsien Chou

Jian-Ru Lin

Yu-Hsiang Chen

An-Ming Lee

Shih-Chun Wei

Chia-Fa Chang

Yan Ning

Pei-Si Wu

Wing Fai Loke

Shao-Szu Ho

Kuan-Chang Tsung

Yo-Hao Tu

Chinchi Chang

Joseph Gerchih Chou

Cheng-Hsian Li

Bin Wan

Ming-Je Tsai

Salma Elabd

Tzu-Hsien Sang

Juan Xie

Ahmed Kord

Wenbo Xu

Pohboon Leong

A crystal oscillator having a voltage regulator configured to receive a first power supply voltage and output a second power supply voltage; a source follower configured to receive the second power supply voltage and output a third power supply voltage in accordance with a control voltage; a first inverter operating under the third power supply voltage and configured to receive a first oscillatory signal from a first node and output a second oscillatory signal at a second node; a second inverter operating under the third power supply voltage and configured to output a third oscillatory signal; a crystal placed across the first node and a second node; a first shunt capacitor configured to shunt the first node to ground; a second shunt capacitor configured to shunt the second node to ground; and a clocked lowpass filter configured to output the control voltage in accordance with the pulsed signal.

Low noise crystal oscillator

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

Phase lock loop having low clock jitters

A method operates by receiving an input signal; transforming the input signal into a first transformed signal of a common-mode voltage equal to a first bias voltage; transforming the input signal into a second transformed signal of a common-mode voltage equal to a second bias voltage; detecting a peak of the first transformed signal and making the first bias voltage equal to a sum of a first DC (direct current) voltage and a first dynamic voltage; detecting a valley of the second transformed signal and making the second bias voltage equal to a sum of a second DC voltage and a second dynamic voltage; amplifying the first transformed signal into a first output signal across a first load using a N-type cascode amplifier; and amplifying the second transformed signal into a second output signal across a second load using a P-type cascode amplifier.

Power efficient complementary amplifier and method thereof

A method of envelope detection receives an RF (radio frequency) signal comprising a first voltage and a second voltage; converts the first voltage into a first current using a first VCCS (voltage controlled current source); converts the second voltage into a second current using a second VCCS; converts a bias voltage into a third current using a third VCCS; converting an output voltage into a fourth current using a fourth VCCS; sums the first current and the second current into an input current flowing through a first internal node of a first internal voltage; sums the third current and the fourth current into a mirrored current flowing through a second internal node of a second internal voltage; uses a source follower to receive the second internal voltage and output the output voltage; and uses a current mirror to force the mirrored current to be equal to the input current.

Envelope detector and method thereof

A radio frequency integrated circuit (RFIC) includes a transmitter, a receiver, a first pin electrically shorted to a first node wherein the transmitter and the receiver are connected, and a second pin electrically shorted to a second node within the receiver. The RFIC is soldered on a printed circuit board (PCB). In a transmitter-receiver co-share configuration, the first pin is terminated with a high-impedance component on the PCB. In a transmitter-receiver split configuration, the first pin and the second pin are coupled through an external capacitor on the PCB.

Configurable radio transceiver and method thereof

A clock transmission circuit includes a voltage-to-current converter configured to convert a first clock into a first current; a transmission line configured to convey the first current into a second current; a transformer comprising a primary inductor and a secondary inductor and configured to convert the second current received via the primary inductor into a second clock output via the secondary inductor; a tuning capacitor configured to form a resonance with the secondary inductor; and a regenerative network connected to the secondary inductor and configured to provide a negative resistance to reinforce the resonance.

Apparatus and method of power efficient high-speed clock transmission

A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.

Low-noise speedy duty cycle detector and method thereof

A charge pump includes a DAC (digital-to-analog converter) configured to draw a first current and a second current from a first node and a second node, respectively, in accordance with a first logical signal, a second logical, and a B-bit control word; a common-gate amplifier configured to provide a path for charge transfer between the second node and a third node in accordance with a third logical signal; an integrating capacitor connected to the second node and configured to be either discharged by the DAC or charged by the common-gate amplifier in accordance with a fourth logical signal; and a low-impedance active load connected to the first node.

Charge pump for fractional-n frequency synthesizer

A self-loopback radio transmitter having a transmitter with a modulator configured to up-convert a first baseband signal into a first RF (radio frequency) signal in accordance with a first LO (local oscillator) signal, and a power amplifier configured to receive the first RF signal and output a second RF signal to be emitted by an antenna and a third RF signal to be looped back, wherein the third RF signal is magnetically coupled from the second RF signal; and a loopback network having a shielded serial inductor configured to receive the third RF signal and output a fourth RF signal, and a demodulator configured to down-convert the fourth RF signal into a second baseband signal in accordance with a second LO signal, wherein the shielded serial inductor has a serial inductor of spiral topology and a coil laid out on a lower metal layer.

Self-loopback radio transmitter

A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.

Four-phase clock buffer of twenty-five percent duty cycle

An method of integrating an oscillator includes incorporating a main inductor and a main capacitor for establishing an oscillation; incorporating two cross-coupling NMOST and two cross-coupling PMOST for sustaining the oscillation; incorporating a first auxiliary inductor and a first auxiliary capacitor for suppressing a noise of the two cross-coupling NMOST; incorporating a second auxiliary inductor and a second auxiliary capacitor for suppressing a noise of the two cross-coupling PMOST; laying out the main inductor symmetrically with respect to a plane of symmetry; laying out the first auxiliary inductor as a parallel connection of two halves that are inside the main inductor and symmetrical with respect to the plane of symmetry; and laying out the second auxiliary inductor as a parallel connection of two halves that are inside the main inductor in a close proximity to the first auxiliary inductor and symmetrical with respect to the plane of symmetry.

Integrated LC oscillator of compact layout and low phase noise and method thereof

A LNA (low-noise amplifier) includes a matching network configured to provide a three-way coupling between an input node, a matched node, and a source node; a gate capacitor configured to provide AC (alternate current) coupling between the matched node and a gate node; a cascode amplifier configured to receive a gate voltage at the gate node and output an output voltage at an output node in accordance with a source degeneration at the source node; and a load network connected to the output node, wherein the matching network having a shunt inductor and a series inductor that are overlapped in layout to have a strong mutual coupling and a source degenerating inductor that is laid out in a close proximity to the shunt inductor to have a strong mutual coupling.

Integrated low-noise amplifier of compact layout

A programmable gain amplifier includes a programmable resistor ladder deployed across Njunction nodes and controlled by N−1 resistor control signals, where Nis an integer greater than one; a common-gate cascode amplifier multiplexer comprising Ncommon-gate cascode amplifiers configured to receive Ninternal voltages at the Njunction nodes and output Noutput currents in accordance with Namplifier control signals, respectively, to an output node that is loaded with a load; and an AC (alternate current) coupling capacitor configured to couple an input node to the first junction node.

Programmable gain amplifier with impedance matching and reverse isolation

An artificial neural network and method are provided. The method includes receiving a set of input voltages; converting a respective input voltage in said set of input voltages into a respective set of local currents using a voltage-to-current conversion; multiplying said respective set of local currents by a respective set of binary signals to establish a respective set of conditionally inverted currents; summing said respective set of conditionally inverted currents into a respective local current; summing all respective local currents into a global current; and converting the global current into an output voltage using a load circuit.

Mixed-signal neurons for neuromorphic computing and method thereof

A method of phase detection includes receiving a reference clock and an input clock having a first input signal and a second input; sampling the first input signal and the second input signal into a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; using a regulated current mirror to convert the first current into the third current; using a first current steering network to steer the second current into either a fourth current or a fifth current in accordance with a pulse signal; using a second current steering network to steer the third current into either a sixth current or a seventh current; connecting a lowpass filter to the output node to establish an output voltage and a lowpass-filtered voltage; and forcing the standby voltage to be equal to the lowpass-filtered voltage using a unity-gain buffer.

Low-offset subsampling phase detector and method thereof

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Fremont, CA, United States of America

Chia-Liang (Leon) Lin