Faraday Technology Corporation

Chia-Liang Lai

Kuan-Yu Chen

Wen-Ching Hsiung

Jeng-Dau Chang

Shen-Iuan Liu

Song-Rong Han

Wei-Ming Lin

Ding-Shiuan Shen

Shao-Ku Kao

Jung-Yu Chang

Cheng-Tao Chang

A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Clock generating apparatus and fractional frequency divider thereof

A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Signal detection circuit with deglitch and method thereof

A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Signal comparison circuit

A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Frequency detection circuit and detection method for clock data recovery circuit

Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.

Over-voltage indicator and related circuit and method

A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N&#x2212;a)(P&#x2212;S) through receiving the frequency divided signal and a control word; wherein N, P, and S are integers, and a, b are fractional numbers, and S can be adjusted by the delta-sigma modulator.

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Changhua County, Taiwan

Chia-Liang Lai