Realtek Semiconductor Inc.

Chia-Liang Chiang

Chao-Cheng Lee

Wen-Chi Wang

Jui-Yuan Tsai

Yu-Pin Chou

Sheng-Nan Chiu

Po-Chiang Wu

Ying-Chuan Peng

Chung-Ting Yang

A test circuit, for checking whether at least one programmable gain amplifier (PGA) operates correctly, includes a signal generator, a gain controller, a test level output circuit, a comparison circuit and an identifying circuit. The signal generator is utilized for outputting a test input signal to a PGA to generate a test output signal. The gain controller is utilized for outputting a gain control signal to the PGA to adjust a gain of the PGA. The test level output circuit is utilized for referring to the test output signal to output a first test level and a second test level. The comparison circuit is utilized for comparing the first and second test levels to generate a result signal. The identifying circuit is utilized for identifying whether the PGA operates correctly according to the result signal.

Test circuit for programmable gain amplifier

A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.

Phase locked loop with nonlinear phase-error response characteristic

A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Pipeline ADC calibrating method and apparatus thereof

A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

Error measuring method for digitally self-calibrating pipeline ADC and apparatus thereof

A low-to-high level shifter operating under a first supply voltage is disclosed. The low-to-high level shifter includes a pull-down circuit coupled to an input signal, the pull-down circuit having a plurality of low-voltage devices, the input signal corresponding to a second supply voltage; and a pull-up circuit coupled to the pull-down circuit, the pull-up circuit having a plurality of high-voltage devices. The low-to-high level shifter generates an output signal according to the input signal, the output signal corresponds to the first supply voltage, and the first supply voltage is larger than the second supply voltage.

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Taipei Hsien, Taiwan

Chia-Liang Chiang