Ememory Technology Inc.

Quanta Computer Incorporated

Chia-Jung Hsu

Wein-Town Sun

Chun-Yuan Lo

Wei-Ren Chen

Chun-Hsiao Li

Yi-Chieh Liu

Shen-Pu Hsieh

Chin-Kuo Wang

Tsung-Mu Lai

Chia-Fu Chang

Yu-Hsiung Tsai

Che-Wei Chang

Woan-Yun Hsiao

Jui-Ming Kuo

Chang-Chun Lung

A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

Manufacturing method for nonvolatile charge-trapping memory apparatus

An electronic device with a receiving function is provided. The electronic device is adapted to receive and shift out an object. The electronic device includes a device housing, an actuating unit, a linkage unit and a holder. The actuating unit is disposed in the device housing. The linkage unit is connected to the actuating unit, wherein the actuating unit is adapted to move the linkage unit. The holder is connected to the device housing and the linkage unit, wherein the holder is adapted to be rotated between an extended orientation and a received orientation relative to the device housing, and the object is detachably connected to the holder.

Electronic device with receiving function

A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Programming method of non-volatile memory cell

A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.

Memory cell of charge-trapping non-volatile memory

A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.

Memory structure and operation method thereof

A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Memory device and method for operating memory device

A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.

Memory cell array of programmable non-volatile memory

A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

Memory device including alignment layer and semiconductor process method thereof

A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.

Memory device capable of improving erase and program efficiency

An external display module is provided, which is adapted to be detachably connected to an electronic device. The external display module includes a module base and a first screen unit. The module base includes a first base side, two first tracks and at least one first slot. The first screen unit is rotatably connected to the module base, wherein the first screen unit includes a first screen, a first shaft, at least one first guiding member and two first blocks, the first shaft is disposed on the edge of the first screen unit, the first guiding member is affixed to the first shaft and is rotated with the first shaft, the first block is connected to the first shaft, the first guiding member is inserted into the first slot and is guided by the first slot, and the first block is adapted to slide in the first track.

External display module

A notebook computer is provided. The notebook computer includes a device body, a cover and a media unit. The device body includes a first body housing and a second body housing, wherein the second body housing pivots on the first body housing. The cover pivots on the first body housing and is slidably connected to the second body housing. When the cover is rotated from a folded state to an unfolded state relative to the device body, the second body housing is pushed to rotate from the first housing orientation to the second housing orientation relative to the first body housing. The media unit pivots on the first body housing and is slidably connected to the second body housing.

Notebook computer

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate

A notebook computer includes an upper part, a lower part, a delay linkage module, and a hinge portion connected to the lower part and the upper part. The delay linkage module includes a delay linking rod, a linkage member, a guide rod and a connecting shaft. The linkage member is fixedly connected to the hinge portion, and pivotally connected to the delay linking rod. The guide rod is pivotally connected to a second display screen and a fixing base of the lower part. The connecting shaft is connected to the guide rod, and slidably located in an elongated through hole of the delay linking rod. when a first display screen of the upper part is rotated away from the lower part, the hinge portion pulls the delay linkage module to rotate the second display screen being lifted up from the lower part.

A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.

Memory structure and programing and reading methods thereof

A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.

Growing community of inventors

Taoyuan, Taiwan

Chia-Jung Hsu