Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Richtek Technology Corporation

Tsinghua University

Chia-Jung Chang

Chia-Hui Chen

Hsiang-Hui Cheng

Jing-Yuan Lin

Jam-Wem Lee

Li-Wei Chu

Wan-Yen Lin

Chih-hao Hsu

Yu-Kai Tsai

Yu-Ti Su

Chia-Wei Hsu

Ming-Fu Tsai

Po-Lin Peng

Shu-Yu Su

Shao-Te Wu

Jui-Hung Tsai

Shih-Peng Chang

Ching-Hsi Nan

Fu-Ching Hsu

Yu-Sheng Hsieh

Ying-Hao Wang

Jiing-Horng Wang

Shao-Ming Chang

Yu-Pin Tseng

Tsan-He Wang

Wun-Jie Lin

Bo-Ting Chen

Fan-Gang Tseng

Yu-Sheng Huang

Jien-Ming Chen

Yu-Lun Chueh

Chih-Hao Hsu

Chun-Kai Mao

Cheng-Yu Liu

Yu-Hsiu Fu

Chiu-Yun Tsai

Chien-Lien Peng

Wen-Chih Chang

Horn-Chin Lee

Tso-Yu Wu

Hsiang-Feng Yu

Chia-Wei Kuo

Ryota Terauchi

Chieh-Shiung Chang

Yu-An Chang

A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.

Switching regulator and control method thereof

A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Switching regulator and operation clock signal generator circuit and control method thereof

Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

ESD power clamp devices and circuits

The present disclosure provides a semiconductor device, which includes a process monitor circuit, a controller, and an output buffer. The process monitor circuit is configured to measure process information of the semiconductor device. The controller is electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information. The output buffer is electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code.

Slew rate controlled output buffer circuit and semiconductor device

Circuits and methods are provided for an input hysteresis buffer that includes a voltage limiting unit, a voltage detecting unit connected to the voltage limiting unit, and a supply tracking bias unit connected to the voltage detecting unit. The voltage liming unit comprises a first voltage limiting unit and a second voltage limiting unit. The voltage detecting unit comprises a first voltage detecting unit configured to detect the presence of a first threshold voltage in an input signal, and a second voltage detecting unit configured to detect the presence of a second threshold voltage in the input signal. The supply tracking bias unit is configured to supply a control signal to the voltage detecting unit.

Input hysteresis buffer in overdrive design

Systems and methods are provided for an electronic device that comprises a core logic circuit coupled to a supply voltage rail and an operating voltage rail. During a standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and a post driver voltage rail has an overdrive voltage that is greater than the operating voltage. The electronic device further comprises a first power clamp circuit coupled to the supply voltage rail and the post driver voltage rail, a low-side logic-high voltage rail coupled to the first end of the core logic circuit, and a first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. The first power-to-power clamp circuit is configured to receive electrostatic discharge (ESD) current between the post driver voltage rail and the low-side logic-high voltage rail.

Overdrive I/O ESD protection network

An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.

Semiconductor device with ESD protection and methods of operating and configuring the same

A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.

Voltage tracking circuit and method of operating the same

A method includes calculating a processing tool offset for a processing tool, wherein the processing tool offset is a first portion of a process offset time attributable to a processing tool. The method further includes calculating a product offset, wherein the product tool offset is a second portion of the process offset time attributable to a product. The method further includes determining whether the product offset is stable based on a pre-determined tolerance and a number of processed wafers. The method further includes calculating an offset time for processing the product using the processing tool based on the calculated processing tool offset, without considering the product offset in response to a determination that the product offset is stable.

Method of making semiconductor devices and control system for performing the same

A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

Method for operating semiconductor device including multi-gated I/O system

Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Electrostatic discharge protection

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Level shifter

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Device and method for operating the same

A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.

Optical water-quality detection apparatus

Growing community of inventors

Hsinchu, Taiwan

Chia-Jung Chang