Realtek Semiconductor Inc.

Chia-Jun Chang

Ka-Un Chan

Chao-Cheng Lee

Ying-Hsi Lin

Hsien-Ku Chen

Chia-Yi Lee

Po-Chih Wang

Chih-Lung Chen

Kuan-Yu Shih

Tzung-Ming Chen

Pei-Ju Chiu

Yi-Ching Wu

Yang Chang

Ping-Hsuan Tsai

Jon-Jin Chen

A radio frequency transceiver device includes an antenna unit, a first matching circuit, a receiver circuit, a second matching circuit, a transmitter circuit, and an auxiliary circuit. The receiver circuit includes a mixer unit. The auxiliary circuit includes a first transformer coil and a second transformer coil. The first matching circuit and the receiver circuit are configured to form a first signal reception channel to receive, process, and transmit the first radio frequency signal to the mixer unit when the first radio frequency signal is a high gain radio frequency signal. The second matching circuit and the auxiliary circuit are configured to form a second signal reception channel to receive, process, and transmit the first radio frequency signal to the mixer unit when the first radio frequency signal is a middle-low gain radio frequency signal. Another radio frequency signal transceiver device further includes a third matching circuit.

Radio frequency transceiver device

An inductor device includes a first inductor, a second inductor, and at least one switch circuit. The second inductor is arranged to enclose the first inductor, and use a topmost layer metal to resist external interference for the first inductor. The at least one switch circuit is coupled to the second inductor, and is arranged to receive at least one control voltage, wherein the at least one control voltage is arranged to adjust conduction degree of the at least one switch circuit.

Inductor device that can resist external interference and adjust inductance value and quality factor of inductor

A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

Communication chip

A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

Low noise amplifier circuit having multiple gains

Disclosed is a radio-frequency (RF) circuit capable of performing an RF characteristic test in a test mode. The RF circuit includes: a test signal generator generating a test signal; an RF receiver, coupled to the test signal generator, transmitting the test signal and thereby generating a receiver analog signal; a coupling circuit transmitting the receiver analog signal to an RF transmitter in the test mode; the RF transmitter transmitting the receiver analog signal and thereby generating a transmitter analog signal; a test result generator, coupled between the RF transmitter and a test result output terminal, including a signal converter for generating a converted signal according to the transmitter analog signal in the test mode, wherein the output signal at the test result output terminal is the converted signal or originated therefrom and relates to the result of the RF characteristic test.

Radio-frequency circuit

An amplifying circuit includes a first gain adjusting circuit, a second gain adjusting circuit, a load circuit and a switch module. When the amplifying circuit operates in a first mode, the first gain adjusting circuit receives a first input signal, and generates a first output signal to a second output terminal of the amplifying circuit via the load circuit and the switch module; and when the amplifying circuit operates in a second mode, the second gain adjusting circuit receives a second input signal, and generates a second output signal to a first output terminal of the amplifying circuit via the load circuit and the switch module.

Amplifying circuit and associated receiver

A signal converting circuit includes: a first switching circuit; a second switching circuit; and a first balance-unbalance circuit (Balun) having a first signal terminal coupled to an antenna, a second signal terminal coupled to the first switching circuit, and a third signal terminal coupled to the second switching circuit; wherein when the first balance-unbalance circuit operates in a first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a first signal processing circuit, and when the first balance-unbalance circuit does not operate in the first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a reference voltage.

Signal converting circuit capable of reducing/avoiding signal leakage and related signal converting method

An amplifier includes a transformer and a first stage gain circuit. The transformer includes a primary coil and a secondary coil. The primary coil is utilized for receiving an input signal. The first stage gain circuit has a first input port, which is coupled to the primary coil. The first stage gain circuit is utilized for gaining the input signal so as to generate a first output.

Amplifier with gain circuit coupeld to primary coil of transformer

A signal amplifying circuit includes: an input stage circuit, arranged to receive an input signal; a first inductive device coupled between the input stage circuit and a first reference voltage; an output stage circuit arranged to generate an output signal according to the input signal; and a second inductive device coupled between the output stage circuit and a second reference voltage, wherein at least a part of a winding of the first inductive element is cross-coupled to at least a part of a winding of the second inductive element.

Signal amplifying circuit with reduced output signal noise by introducing coupling effect and related method thereof

A signal transmitting/receiving circuit includes a transmitter, a receiver, a balun and an impedance matching circuit. The transmitter is utilized for transmitting an output signal. The receiver is utilized for receiving an input signal. The balun includes a first input terminal, a second input terminal and an output terminal. The impedance matching circuit, which is coupled between the transmitter, the receiver, and the balun, provides transmitting impedance when the transmitter transmits the output signal such that an output signal may be output at an output terminal of the balun via a transmitting path. Also, the impedance matching circuit provides transmitting impedance when the receiver receives the input signal such that the input signal may be transmitted from the output terminal of the balun to the receiver via a receiving path.

Signal transmitting/receiving circuit including an impedance matching circuit

A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Receiving device and related method for calibrating DC offset

The present invention discloses an impedance calibration circuit and method for calibrating an equivalent impedance of a semiconductor circuit element. The disclosed impedance calibration circuit includes a reference circuit, a second circuit element, and a controlling circuit. The reference circuit receives a test signal and outputs a first signal. The second circuit element is coupled to the semiconductor circuit element to form a test circuit and receives the test signal and outputs a second signal. The controlling circuit is coupled to the reference circuit and the test circuit for comparing the first signal with the second signal and adjusting the equivalent impedance of the semiconductor circuit element accordingly.

Impedance calibration circuit and method thereof

An amplifying circuit includes a differential amplifier having a positive input end, a negative input end, a positive output end, and a negative output end; a first input impedance coupled between the negative input end and a first input signal; a second input impedance coupled between the positive input end and the first input signal; a third input impedance coupled between the negative input end and a second input signal; a fourth input impedance coupled between the positive input end and the second input signal; a first output impedance coupled between the negative input end and the positive output end; a second output impedance coupled between the negative input end and the negative output end; a third output impedance coupled between the positive input end and the positive output end; and a fourth output impedance coupled between the positive input end and the negative output end.

Amplifying circuit

A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

Low pass filter

The invention is to provide a receiving end architecture comprising a variable gain amplifier, for outputting a pair of differential signals comprising a first signal and a second signal via a first and a second outputs respectively according to the receiving signal through adjusting the amplitude of the receiving signal; a mix-type sample-and-hold circuit for outputting a first sampled signal via a first end and a second sampled signal via a second end and then outputting the second sampled signal via the first end and the first sampled signal via the second end through performing sample-and-hold on the pair of differential signals; and an analog/digital converter coupled to the mix-type sample-and-hold circuit for generating a digital signal according to the first and the second sampled signals.

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Taipei, Taiwan

Chia-Jun Chang