Broadcom Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Chia-Jen Hsu

Desheng Ma

Hui Pan

Derek Hing Sang Tam

Preeti Mulage

Chun-Ying Chen

Young J Shin

Derek Tam

Ryan Michael Desrosiers

Xin Wang

Russell Eliot Radke

Joseph Aziz

Rong Wu

Tianwei Li

Yuan Yao

Tao Wang

Xin Jin

Wei-Ta Shih

Dae Woon Kang

Karthik Raviprakash

A wireless power receiver includes circuitry configured to receive a wirelessly induced voltage from a wireless power transmitter via a magnetically induced connection with the wireless power transmitter. It is determined that an overvoltage condition exists when the wirelessly induced voltage exceeds a threshold voltage, and the wirelessly induced voltage is reduced in response to determining that the overvoltage condition exists. The circuitry communicates the overvoltage condition to the wireless power transmitter via the magnetically induced connection while over-voltage protection is enabled.

Wireless power receiver voltage control enabling simultaneous communications to transmitter in over-voltage state

An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.

Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity

An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity

A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.

Pipelined interpolating sub-ranging SAR analog-to-digital converter

Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid.

Power efficient driver architecture

A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

System and method for integration of hybrid pipeline

Growing community of inventors

Irvine, CA, United States of America

Chia-Jen Hsu