United Microelectronics Corp.

National Chi Nan University

Fujian Jinhua Integrated Circuit Co., Ltd.

Academia Sinica

Naitonal Chi Nan University

Chia-Hung Wang

Tai-Ping Sun

En-Chiuan Liou

Chien-Hao Chen

Sho-Shen Lee

Yi-Ting Chen

Jhao-Hao Lee

Chien-Wei Huang

Yu-Cheng Tung

Chi-Huey Wong

Feng-Yi Chang

Fu-Che Lee

Chung-Yi Wu

Chia-Chang Hsu

Chun-Chi Yu

Yu-Chan Chao

Yuan-Chi Pai

Chia-Hsun Tseng

Yi-Wang Zhan

Chia-Ching Lin

Yi-Jing Wang

Chia-Liang Liao

Che-Yi Lin

Teng-Chin Kuo

Tuan-Yen Yu

Jia-Yu Chen

Wei-Shun Cheng

Heng-Yu Yan

Tzu-Lun Hung

Carol Pei Yin Wu

Yueh-Lung Wu

Li-Wen Mao

Huei-Jyun Lin

Jia-Hao Li

Shiou-Ting Li

Chih-Yu Chiang

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Manufacturing method for semiconductor pattern

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Method of forming layout of semiconductor device

A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

Semiconductor structure

Described herein are synthetic glycan conjugates comprising a carrier and a glycan moiety derived from, wherein the glycan moiety is covalently linked to the carrier through a linker. Also provided herein are a mixture of the glycan conjugates thereof, immmunogenic compositions thereof, and kits thereof. The invention further provides methods of using the synthetic glycan conjugates and immunogenic compositions thereof to treat and/or reduce the risk of infectious diseases such as bacterial infections. 

Glycan conjugates and use thereof

A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

Method of forming integrated circuit

A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x', y&#x2032;); and (d) calculating a process parameter from the revised overlay datum (x&#x2032;, y&#x2032;). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.

Lithography system and semiconductor processing process

An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Overlay marks and semiconductor process using the overlay marks

A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Method of correcting overlay error

A light emitting system includes: a voltage detecting unit connected across a solid-state light emitting component for detecting a forward voltage thereof and generating a detection voltage having a magnitude dependent on the forward voltage; a current control unit connected to the light emitting component for controlling, according to a compensation voltage, flow of an operating current, which has a magnitude dependent on the compensation voltage, therethrough; and a compensation voltage module connected to the voltage detecting unit and the current control unit, disposed to receive a reference voltage, and configured to generate the compensation voltage, which varies according to the forward voltage, for provision to the current control unit according to the detection voltage, an operating voltage having a magnitude dependent on the operating current, and the reference voltage.

Light emitting system with light emitting power stabilization

An illumination system includes: a signal receiver device configured to, in response to a coupling signal, generate a receiver-side signal frame including a control code portion based on control information of the coupling signal; a code extracting unit operable to extract the control code portion from the receiver-side signal frame; and a current providing unit operable to provide a driving current through a light emitting component according to the control code portion extracted from the code extracting unit. The driving current has a magnitude dependent on the extracted control code portion.

Illumination system, and driving device and signal transmitter device thereof

A light power compensation circuit includes a current source to be electrically coupled to a temperature-detecting light-emitting device and providing a working current for the temperature-detecting light-emitting device, a detector unit operable to detect a forward bias voltage across the temperature-detecting light-emitting device and providing a detector voltage proportional to the forward bias voltage, a compensation voltage converting module converting the detector voltage into a compensation voltage which has a negative relation to change in the detector voltage, and a driving module converting the compensation voltage into a driving current which is proportional to the compensation voltage and which drives operation of a controlled light-emitting device.

Light power compensation device, light power compensation circuit, and detecting module

A light emitting system includes: first, second, and reference light emitting components having first, second, and reference forward voltages when driven under constant current, respectively; an instrumentation amplifier for generating a temperature detection voltage with a magnitude dependent on the reference forward voltage of the reference light emitting component; first and second compensation voltage modules each generating a respective one of first and second compensation voltages based at least on the temperature detection voltage; and first and second power control modules providing first and second driving currents through the first and second light emitting components according to the first and second compensation voltages and the first and second forward voltages, respectively.

Light emitting system capable of color temperature stabilization

A light-emitting system includes first and second solid-state light-emitting components, a current source providing a constant current through the second solid-state light-emitting component, a first instrumentation amplifier detecting a second forward voltage across the second solid-state light-emitting component so as to generate a first detection voltage having a magnitude dependent on the second forward voltage, a compensation voltage module operable to generate a compensation voltage having a magnitude related to the second forward voltage according to the first detection voltage and two reference voltages, and a power control module detecting a first forward voltage across the first solid-state light-emitting component and providing a driving current therethrough that is dependent on the compensation voltage and the first forward voltage and that varies according to ambient temperature.

Growing community of inventors

Taichung, Taiwan

Chia-Hung Wang