United Microelectronics Corp.

Chia-Hung Kao

Chin-Cheng Chien

Ming-Sheng Yang

Hal Lee

Alan Cheng

A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.

Method of preventing leakage current of a metal-oxide semiconductor transistor

A method of manufacturing a field effect transistor with a dual-spacer structure. A substrate having a first device region and a second device region is provided. The first device region comprises a first gate formed over the substrate and the second device region comprises a second gate formed over the substrate. A first dielectric layer is formed over the substrate. A second dielectric layer is formed on the first dielectric layer. A portion of the second dielectric layer is removed to expose a portion of the first dielectric layer in the second device region. A portion of the remaining second dielectric layer is removed to form a first spacer on the second dielectric layer on the sidewall of the first gate. A portion of the first dielectric layer is removed to form a second spacer on the sidewall of the second gate. The first spacer and the remaining second dielectric layer between the first spacer and the first gate together form a third spacer.

Method for manufacturing dual-spacer structure

A method of fabricating a capacitor includes formation of a first dielectric layer having a contact hole on a substrate. A conductive layer is formed over the substrate and is electrically coupled with a source/drain region through the contact hole. An isolation layer is formed on the conductive layer. The isolation layer and the conductive layer are patterned to form a patterned isolation layer and a raised region over the contact hole. A first spacer is formed on the sidewall of the patterned isolation layer and the raised region. The patterned isolation layer is removed. The first spacer is used as a mask to etch the conductive layer to form another two sidewalls. The first spacer is removed. Two spacers are formed on the two sidewalls and used as masks. The conductive layer is patterned again to form two raised regions concentrically in shape.

Growing community of inventors

Tai-Nan, Taiwan

Chia-Hung Kao