Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Hui Lin

Shih-Wen Huang

San-De Tzu

Kai Hung Cheng

Cheng-Chung Lin

Baw-Ching Perng

Ai-Sen Liu

Shin-Yeu Tsai

Hong-Hsien Ke

Tai-Chun Huang

Ming-Ta Lei

Yih-Shung Lin

Chung-Ting Ko

Wen-Kai Wan

Jei Ming Chen

Jaming Chang

Chia-Shiung Tsai

Fu-Liang Yang

Shih-Chieh Chang

Chun-Chieh Lin

Lan-Lin Chao

Chun-Yi Lee

Bo-Cyuan Lu

Sung-En Lin

Kuei-Wu Huang

Wei-Zen Chou

Wen-Cheng Wu

Wen-Hong Huang

Yun-Wen Chu

Yih-Hsiung Lin

Dong-Sheng Li

Yao-Hsu Sun

Chanming Hu

Ru-Gun Liu

Chin-Hsiang Lin

Jeng-Horng Chen

Tsai-Sheng Gau

Burn Jeng Lin

Chun-Kuang Chen

Chen-Cheng Kuo

Chien-Hung Lin

Chih-Chiang Tu

Jr-Hung Li

Joung-Wei Liou

Hua-Tai Lin

Szu-An Wu

Chui-Ya Peng

Ming-Te Chen

Ting-Gang Chen

Fu-Jye Liang

Chien-Feng Lin

Jen-Chieh Shih

Chung-Hsing Chang

Chieh-Ping Wang

Bang-Ching Ho

Ching-Yu Chen

Chih-Cheng Chin

Ching-Shiun Chiu

Ying-Hsiu Tsai

Ching-Chia Lin

Tsang-Yu Liu

Cheng-Liang Chang

Chun Ming Wang

Hung Jui Kuo

Shih-Chiang Tu

Yin-Ping Lee

Burn-J Lin

Ming-Dai Lei

A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

Semiconductor structure

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Semiconductor Fin cutting process and structures formed thereby

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Semiconductor device and method of manufacture

Semiconductor fin cutting process and structures formed thereby

A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.

Semiconductor structure with barrier layer and method for forming the same

A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

Semiconductor device and method

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

Cut metal gate devices and processes

Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

Semiconductor device structure and method for forming the same

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Forming doped regions in semiconductor strips

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

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Dajia, Taiwan

Chia-Hui Lin