Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Hui Chen

Chia-Jung Chang

Wan-Yen Lin

Kuo-Ji Chen

Tsung-Hsin Yu

Wei Yu Ma

Lee-Chung Lu

Jam-Wem Lee

Wun-Jie Lin

Ming-Hsiang Song

Li-Wei Chu

Chia-Hung Chu

Yi-Ting Wang

Fang-Tsun Chu

Yu-Ren Chen

Wei-Yu Ma

Tao Yi Hung

Yu-Kai Tsai

Bo-Ting Chen

Po-Hsiang Lan

Guang-Cheng Wang

Chien-Yuan Lee

Tzu-Yi Yang

Tsung-Ju Yang

Systems and methods are provided for an electronic device that comprises a core logic circuit coupled to a supply voltage rail and an operating voltage rail. During a standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and a post driver voltage rail has an overdrive voltage that is greater than the operating voltage. The electronic device further comprises a first power clamp circuit coupled to the supply voltage rail and the post driver voltage rail, a low-side logic-high voltage rail coupled to the first end of the core logic circuit, and a first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. The first power-to-power clamp circuit is configured to receive electrostatic discharge (ESD) current between the post driver voltage rail and the low-side logic-high voltage rail.

Overdrive I/O ESD protection network

An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.

Semiconductor device with ESD protection and methods of operating and configuring the same

In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Circuit and method for high voltage tolerant ESD protection

Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Electrostatic discharge protection

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Level shifter

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

Input buffer circuit

An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.

Three-dimensional integrated circuit having ESD protection circuit

A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

Temperature instability-aware circuit

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generates an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain.

Buffer circuit between different voltage domains

A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.

Method of forming three-dimensional integrated circuit having ESD protection circuit

A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

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Hsinchu, Taiwan

Chia-Hui Chen