Macronix International Co., Ltd.

National Applied Research Laboratories

Tsinghua University

Chia-Hua Ho

Erh-Kun Lai

Kuang-Yeu Hsieh

Hang-Ting Lue

Ming-Daou Lee

Yen-Hao Shih

Tzu-Hsuan Hsu

Hsiang-Lan Lung

Kuang Yeu Hsieh

Shih-Ping Hong

Shih-Chin Lee

Chia-Min Yang

Min-Cheng Chen

Chia-Yi Lin

Bo-Kai Chen

Wen-Cheng Chiu

Cho-Lun Hsu

Mao-Chen Liu

Chang-Hsien Lin

Tung-Yen Lai

A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.

Semiconductor memory storage array device and method for fabricating the same

A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Thin film transistor and fabricating method

A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

Resistance type memory device

A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

Memory cell and process for manufacturing the same

The present invention relates to a method for preparing nitride nanomaterials, including: providing a first precursor and a second precursor, in which the first precursor is a transition metal precursor, a group IIIA precursor, a group IVA precursor or a mixture thereof, and a second precursor is a nitrogen-containing aromatic compound; and heating the first precursor with the second precursor to form a nitride nanomaterial. Accordingly, the present invention provides a simpler, nontoxic, more widely applied and low-cost method for preparing nitride nanomaterials.

Method for preparing nitride nanomaterials

A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

Resistive random access memory and method for manufacturing the same

An attenuator is provided. The attenuator includes a first resistor, which is electrically connected to an input node; a nanowire, which is connected to the first resistor in series, for filtering low frequency signal; a second resistor, having an output node, which is electrically connected to the nanowire; wherein when a low frequency voltage is received by the input node, the nanowire filters the low frequency voltage such that the output node generates an output voltage lower than the low frequency voltage.

Attenuator

A method for manufacturing resistive memory includes depositing a first conductive material layer on a substrate; etching the first conductive material layer to form a first signal line with a first surface; forming a memory material layer with a second surface coupled to the first signal line via the second surface contacting the first surface; depositing a second conductive material layer coupled to the memory material layer; etching the second conductive material layer to form a second signal line, wherein the area of the second surface is substantially larger or equal to the area of the overlapping region of the first signal line and the second signal line.

Resistive memory and method for manufacturing the same

A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer.

Method for fabricating memory

Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

Dual-gate, sonos, non-volatile memory cells and arrays thereof

A magnetic memory, a memory cell thereof, and a method of manufacturing the memory cell are provided. The memory cell of the magnetic memory includes a bottom contact layer, a bit line, a magnetic stack structure and a dielectric material. The bit line is disposed over the bottom contact layer. The magnetic stack structure is disposed between the bottom contact layer and the bit line. The dielectric material at least fills between the bottom contact layer and the bit line and surrounds the magnetic stack structure. A gap is formed between the dielectric material and the magnetic stack structure. During programming of the memory cell, the magnetic stack structure generates heat, and the gap delays heat loss.

Magnetic memory and memory cell thereof and method of manufacturing the memory cell

A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure. The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel junction structure, and the volume of the second magnetic tunnel junction structure is smaller than that of the first magnetic tunnel junction structure.

Magnetic random access memory, manufacturing method and programming method thereof

A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

Growing community of inventors

Hsinchu, Taiwan

Chia-Hua Ho