Via Technologies, Inc.

Pegatron Corporation

Chia-Hsing Yu

Nai-Shung Chang

Chi-Hsin Lin

Chia-Hsin Chen

Tsai-Sheng Chen

Shu-Hui Chen

Ching-Fu Chuang

Tsung-Yi Lin

Lin-Hung Chen

Lin Yang

Hsuan-I Wang

Chih-Yuan Liu

Chi-Hsing Lin

Chien-Lun Pan

Mei-Ling Lin

Lie-Wen Chen

The application provides a temperature increasing device and a temperature increasing method. The temperature increasing device is arranged on a motherboard including at least one system element. The temperature increasing device includes a power supply module and a controller After the power supply module is triggered, the power supply module outputs an enable signal to the system element and the controller, the controller detects whether the system element operates according to a preset power-on action, if the controller determines that the system element does not operate according to the preset power-on action, the controller outputs an electric signal to enable the temperature of the system element to increase, and when the temperature of the system element is increased to an extent that the controller determines that the system element is capable of operating according to the preset power-on action, the controller stops outputting the electric signal.

Temperature increasing device and temperature increasing method

A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

Method for reducing power consumption of a computer system in the working state

A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.

Method for increasing the data processing capability of a computer system

An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission channel between the north bridge chip and the system memory for providing extensive data transmission bandwidth. Alternatively, the additional data transmission channel can be specific to the communication between the graphic accelerator in the north bridge chip and the frame buffer in the system memory.

Core logic chip conducting multi-channel data transmission

The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Graphics display architecture and control chip set thereof

A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

Method for determining an operating voltage of floating point error detection

A control chip supporting a plurality of buses and control chip set thereof is provided. A control chip supporting a plurality of buses chooses a type of bus for complying with another control chip based on the bus type thereby, wherein a device and a driving circuit are included. The device generates required controlling timings based on selection pins. The driving circuit enables required transmitting direction of pins based on selection pins per se.

Control chip supporting plurality of buses and control chip set thereof

A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

Motherboard with reduced power consumption

An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Zand AKof the Socket-central processing unit to determine which type the Socket-central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.

Apparatus and method for supporting multi-processors and motherboard of the same

According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.

Computer system using an interfacing circuit to increase general purpose input/output ports

This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Layout structure for providing stable power source to a main bridge chip substrate and a motherboard

A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.

Power controller and associated multi-processor type supporting computer system

An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.

Power management integrated circuit for overriding an internal frequency ID code of a processor and for providing frequency ID value to a bridge chipset

An accelerated graphic port (AGP) system uses several control signals to allow an AGP graphic card to enter into negotiation with a motherboard. These control signals can drive the motherboard to provide AGP operating voltage (VCCQ) and providing a first reference voltage for the motherboard according to the AGP operating voltage. On the other hand, the motherboard will provide a second reference voltage to the AGP graphic card according to the determination of whether or not the AGP graphic card is an AGP8X card. Therefore the universal AGP connector of the present invention can enable all kinds of AGP graphic cards to be coupled to the motherboard, and can prompt the motherboard to meet with all the AGP system specifications and support all kinds of AGP graphic cards.

Growing community of inventors

Taipei Hsien, Taiwan

Chia-Hsing Yu