Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Hsing Chen

Cheng-Jye Liu

Ming-Hung Chou

Yue-Der Chih

Hung-Cheng Sung

Tai-Liang Hsiung

Chen-Chin Liu

Smile Huang

Chun-Hsiung Hung

Han-Sung Chen

Samuel C Pan

Kent Kuohua Chang

Jiunn-Ren Hwang

Chun-Jung Lin

Tung-Cheng Kuo

Mam-Tsung Wang

Tseng-Yi Liu

Jiann-Long Sung

Samuel Cheng-Sheng Pan

Jiunn-Liang Li

Minnie Hsiung

Liu Cheng-Jye

A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors.

Method of converting between non-volatile memory technologies and system for implementing the method

A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

A method for fabricating a nitride read-only memory is described. An ONO stacked layer and a protective layer are sequentially formed on a substrate. A patterning/etching process is performed to pattern the protective layer and the ONO stacked layer to expose a portion of the substrate. Thereafter, the protective layer is removed by using wet etching. An ion implantation is performed to form buried bit lines in the exposed substrate, and then an insulator is formed on each buried bit line. A plurality of word lines are formed on the substrate crossing over the buried bit lines.

Method for fabricating nitride read-only memory

A method for preventing bit line to bit line leakage in a memory cell is described. In this method, P-implantation is applied to suppress the leakage current induced by the damage, wherein the damage is caused by the etching step for the formation of spacers. The P-implantation step is performed after the etching step, and such a sequence centralizes the implanted ions to prevent them from decreasing the threshold voltage. On the other hand, the P-implantation step is performed after the bit line annealing step to prevent the implanted ions from being thermally diffused.

Method for preventing bit line to bit line leakage in memory cell

A coding method of a multi-level cell, applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2 levels with respect to 2 codes. Each code is constructed with n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, the multi-level memory cell has a specified level for corresponding code to be stored. The relationship is a correspondence between the 2 codes and the 2 levels. Two codes corresponding to any neighboring two levels has only a one-bit difference.

Coding method of multi-level memory cell

A method for determining the necessity for refreshing memory cells of a flash memory that includes providing a first reference memory cell, measuring a current of the first reference memory cell, providing a second reference memory cell, measuring a current of the second reference memory cell, measuring a cell current of one of the memory cells of the flash memory, comparing the measured cell current to the current of the first reference memory cell, comparing the measured cell current to the current of the second reference memory cell, and refreshing the memory cell when the measured cell current is greater than the current of the first reference memory cell but less than the current of the second reference memory cell.

Sensing method for EEPROM refresh scheme

A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed, wherein the the word line voltages are arbitrated according to the threshold voltages of the neighbor bits adjacent to the bits. Next, the bits, to which a same word line voltage should be applied, in the memory cells are distributed to a group of bits with the same word line voltage. Then, the same word line voltage is applied to the bits of the group of bits with the same word line voltage.

Method for compensating a threshold voltage of a neighbor bit

The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavy doping. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current require for Channel Hot Electron Injection (CHEI) programming. Furthermore, before erasing the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.

Method for operating a NROM device

A silicon nitride read only memory and associated method of data programming and erasing. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semiconductor substrate, a first type ion-doped gate conductive layer over the ONO layer and a second type ion doped source/drain region in the substrate on each side of the ONO layer, wherein the second type ions have an electrical polarity opposite to the first type ions. Data is programmed into the silicon nitride read only memory by channel hot electron injection and data is erased from the silicon nitride read only memory by negative gate channel erase method. Since the gate conductive layer and the channel layer are identically doped, the energy gap between the two layers reduced. Hence, operating voltage of the gate terminal is lowered and damage to the tunnel oxide layer by hot holes is reduced.

Silicon nitride read only memory structure and method of programming and erasure

A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.

Method for forming nitride read only memory

A fabrication method for a mask read-only memory includes forming an oxide layer on a provided substrate. A first mask layer is formed on the oxide layer, followed by performing a first ion implantation to form a plurality of equally spaced bit lines. A thermal process is further conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is formed on the denser oxide layer. A second mask layer is formed on the plurality of the word lines, exposing the channel to be coded. A second ion implantation is conducted on the channel to complete the fabrication of the mask read-only memory device.

Method for fabricating a mask read-only memory

A method of fabricating silicon nitride read only memory. A trapping layer is formed on a substrate. Next, a patterned photoresist layer is formed, and the substrate region at the lower section of the trapping layer masked by the photoresist layer is defined as a channel region. The substrate region at the lower section of the trapping layer and no masked by the photoresist layer is defined as a source/drain region. Next, a pocket ion implantation is performed while using the photoresist layer as amask, and a first dopant is implanted into the source/drain region of the substrate. The photoresist layer is used as a mask and the source/drain ions are implanted. A second dopant is implanted into the source/drain region of the substrate. After that, the photoresist layer is removed. Next, the trapping layer is used as a mask, and a thermal process is performed so that the substrate surface of the source/drain region forms a buried source/drain oxide layer, while at the same time, the second dopant at the lower section of the buried source/drain oxide layer forms a buried source/drain. The first dopant forms the pocket doping region at the edge of the channel region of the buried source/drain periphery as a result of thermal diffusion. Finally, a conductive gate is formed on the substrate.

Method of fabricating silicon nitride read only memory

A method of stabilizing a reference bit of a multi-bit memory cell. A first bit of a multi-bit memory cell is pre-programmed to high during fabrication. While reading the multi-bit memory cell, another bit other than the first bit is read as a reference bit.

Method of stabilizing reference bit of multi-bit memory cell

The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC H ) ), under the condition of 300 mTorr and 200-650&deg; C., to form a tantalum pentaoxide (Ta O ) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.

Growing community of inventors

Hsinchu, Taiwan

Chia-Hsing Chen