Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Hsin Hu

Sun-Jay Chang

Min-Chang Liang

Jaw-Juinn Horng

Shien-Yang Wu

Hsueh-Shih Fan

Chung-Hui Chen

Chung-Chieh Yang

Po-Nien Chen

Chung-Peng Hsieh

Huan-Tsung Huang

Yu-Chiun Lin

Yi-Hsuan Chung

Wen-Hsing Hsieh

Ching-Fang Huang

Amit Kundu

A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Semiconductor device and a method for fabricating the same

The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.

Epi block structure in semiconductor product providing high breakdown voltage

The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

Temperature compensation circuits

A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack.

Guard rings including semiconductor fins and regrown regions

A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features.

Method for FinFET integrated with capacitor

A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.

Fin-type resistor

A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.

Bipolar junction transistor formed on fin structures

Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.

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Changhua, Taiwan

Chia-Hsin Hu