Realtek Semiconductor Inc.

Chia-Hsien Cheng

I-Chang Wu

Chihtung Chen

Yi-Te Yeh

Huai-Yu Yen

A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

Growing community of inventors

Hsinchu, Taiwan

Chia-Hsien Cheng