Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Chia-Hsiang Chang

Ting-Hao Wang

Po-Shing Yu

Igor Elkanovich

Ting-Hsu Chien

Tsai-Ming Yang

Yen-Chung Tony Chen

Amnon Parnass

Chun-Chi Chang

Jun-Chen Chen

Yen-Chung Chen

Pei Yu

Jia-Liang Chen

Yuan-Hung Lin

Chung-Kai Wang

Li-Hua Lin

Yu-Ju Chang

Ting-Chin Cho

Wen-Lung Tu

Chao-Ching Huang

Li-Ya Tseng

Wei-An Liang

Yen-Wei Chen

Zanyu Yang

Chun-Hsu Chen

An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180&#xb0; with respect to a row direction and a column direction.

Interface of integrated circuit die and method for arranging interface thereof

A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.

Circuit of communication interface between two dies and method to manage communication interface

A multi-channel transmission device is provided. The multi-channel transmission device includes a clock generator and a plurality of transmitters. The clock generator generates input clocks. The transmitters operate based on spread spectrum clocks respectively. Each of the transmitters comprises a phase rotator. The phase rotator provides a selection signal and an interpolation signal of multiple bits. The phase rotator selects two of the input clocks as a first selected input clock and a second selected input clock according to the selection signal, and generate a spread spectrum clock according to the interpolation signal, the first selected input clock and the second selected input clock.

Multi-channel transmission device

A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.

Power on detection circuit

A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Gated voltage-controlled oscillator and clock and data recovery circuit

A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators.

The invention provides a clock and data recovery (CDR) circuit, including a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal according to a control signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Clock and data recovery circuit

The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

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Hsinchu, Taiwan

Chia-Hsiang Chang